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Searched refs:OFFSET (Results 1 – 25 of 45) sorted by relevance

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/drivers/net/ethernet/chelsio/cxgb/
A Dpm3393.c39 #define OFFSET(REG_ADDR) ((REG_ADDR) << 2) macro
87 t1_tpi_read(cmac->adapter, OFFSET(reg), data32); in pmread()
93 t1_tpi_write(cmac->adapter, OFFSET(reg), data32); in pmwrite()
591 t1_tpi_write(adapter, OFFSET(0x0001), 0x00008000); in pm3393_mac_create()
592 t1_tpi_write(adapter, OFFSET(0x0001), 0x00000000); in pm3393_mac_create()
593 t1_tpi_write(adapter, OFFSET(0x2308), 0x00009800); in pm3393_mac_create()
595 t1_tpi_write(adapter, OFFSET(0x2320), 0x00008800); in pm3393_mac_create()
596 t1_tpi_write(adapter, OFFSET(0x2321), 0x00008800); in pm3393_mac_create()
597 t1_tpi_write(adapter, OFFSET(0x2322), 0x00008800); in pm3393_mac_create()
598 t1_tpi_write(adapter, OFFSET(0x2323), 0x00008800); in pm3393_mac_create()
[all …]
A Dmy3126.c35 #define OFFSET(REG_ADDR) (REG_ADDR << 2) macro
61 t1_tpi_write(adapter, OFFSET(SUNI1x10GEXP_REG_MSTAT_CONTROL), in my3126_interrupt_handler()
64 OFFSET(SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW), &act_count); in my3126_interrupt_handler()
66 OFFSET(SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW), &val); in my3126_interrupt_handler()
/drivers/gpio/
A Dgpio-mb86s7x.c33 #define OFFSET(x) BIT((x) % 8) macro
50 val &= ~OFFSET(gpio); in mb86s70_gpio_request()
67 val |= OFFSET(gpio); in mb86s70_gpio_free()
82 val &= ~OFFSET(gpio); in mb86s70_gpio_direction_input()
101 val |= OFFSET(gpio); in mb86s70_gpio_direction_output()
103 val &= ~OFFSET(gpio); in mb86s70_gpio_direction_output()
107 val |= OFFSET(gpio); in mb86s70_gpio_direction_output()
119 return !!(readl(gchip->base + PDR(gpio)) & OFFSET(gpio)); in mb86s70_gpio_get()
132 val |= OFFSET(gpio); in mb86s70_gpio_set()
134 val &= ~OFFSET(gpio); in mb86s70_gpio_set()
/drivers/xen/xen-pciback/
A Dconf_space.c182 field_start = OFFSET(cfg_entry); in xen_pcibk_config_read()
183 field_end = OFFSET(cfg_entry) + field->size; in xen_pcibk_config_read()
222 field_start = OFFSET(cfg_entry); in xen_pcibk_config_write()
223 field_end = OFFSET(cfg_entry) + field->size; in xen_pcibk_config_write()
369 field->reset(dev, OFFSET(cfg_entry), cfg_entry->data); in xen_pcibk_config_reset_dev()
389 field->release(dev, OFFSET(cfg_entry), cfg_entry->data); in xen_pcibk_config_free_dev()
415 err = xen_pcibk_field_is_dup(dev, OFFSET(cfg_entry)); in xen_pcibk_config_add_field_offset()
420 tmp = field->init(dev, OFFSET(cfg_entry)); in xen_pcibk_config_add_field_offset()
431 OFFSET(cfg_entry)); in xen_pcibk_config_add_field_offset()
A Dconf_space.h75 #define OFFSET(cfg_entry) ((cfg_entry)->base_offset+(cfg_entry)->field->offset) macro
A Dconf_space_quirks.c58 if (OFFSET(cfg_entry) == reg) { in xen_pcibk_field_is_dup()
/drivers/gpu/nova-core/falcon/hal/
A Dga102.rs58 regs::NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION::OFFSET in signature_reg_fuse_version_ga102()
60 regs::NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION::OFFSET in signature_reg_fuse_version_ga102()
62 regs::NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION::OFFSET in signature_reg_fuse_version_ga102()
/drivers/gpu/nova-core/regs/
A Dmacros.rs106 register!(@common $name @ $alias::OFFSET $(, $comment)?);
108 register!(@io $name @ $alias::OFFSET);
128 register!(@common $name @ $alias::OFFSET $(, $comment)?);
130 register!(@io $name @ + $alias::OFFSET);
147 pub(crate) const OFFSET: usize = $offset;
/drivers/gpu/drm/amd/amdgpu/
A Dnbio_v7_11.c74 OFFSET, doorbell_index); in nbio_v7_11_sdma_doorbell_range()
99 OFFSET, doorbell_index); in nbio_v7_11_vpe_doorbell_range()
124 GDC0_BIF_VCN0_DOORBELL_RANGE, OFFSET, in nbio_v7_11_vcn_doorbell_range()
181 GDC0_BIF_IH_DOORBELL_RANGE, OFFSET, in nbio_v7_11_ih_doorbell_range()
A Dumsch_mm_v4_0.c190 data = REG_SET_FIELD(data, VCN_AGDB_CTRL0, OFFSET, in umsch_mm_v4_0_aggregated_doorbell_init()
196 data = REG_SET_FIELD(data, VCN_AGDB_CTRL1, OFFSET, in umsch_mm_v4_0_aggregated_doorbell_init()
202 data = REG_SET_FIELD(data, VCN_AGDB_CTRL2, OFFSET, in umsch_mm_v4_0_aggregated_doorbell_init()
208 data = REG_SET_FIELD(data, VCN_AGDB_CTRL3, OFFSET, in umsch_mm_v4_0_aggregated_doorbell_init()
221 data = REG_SET_FIELD(data, VCN_UMSCH_RB_DB_CTRL, OFFSET, ring->doorbell_index); in umsch_mm_v4_0_ring_start()
A Dnbio_v7_0.c76 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); in nbio_v7_0_sdma_doorbell_range()
93 BIF_MMSCH0_DOORBELL_RANGE, OFFSET, in nbio_v7_0_vcn_doorbell_range()
122 …ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index… in nbio_v7_0_ih_doorbell_range()
A Dnbio_v7_7.c74 OFFSET, doorbell_index); in nbio_v7_7_sdma_doorbell_range()
95 GDC0_BIF_VCN0_DOORBELL_RANGE, OFFSET, in nbio_v7_7_vcn_doorbell_range()
153 GDC0_BIF_IH_DOORBELL_RANGE, OFFSET, in nbio_v7_7_ih_doorbell_range()
A Dnbio_v7_2.c117 OFFSET, doorbell_index); in nbio_v7_2_sdma_doorbell_range()
138 GDC0_BIF_VCN0_DOORBELL_RANGE, OFFSET, in nbio_v7_2_vcn_doorbell_range()
195 GDC0_BIF_IH_DOORBELL_RANGE, OFFSET, in nbio_v7_2_ih_doorbell_range()
A Dnbio_v2_3.c121 BIF_SDMA0_DOORBELL_RANGE, OFFSET, in nbio_v2_3_sdma_doorbell_range()
144 BIF_MMSCH0_DOORBELL_RANGE, OFFSET, in nbio_v2_3_vcn_doorbell_range()
193 BIF_IH_DOORBELL_RANGE, OFFSET, in nbio_v2_3_ih_doorbell_range()
A Dnbio_v6_1.c97 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); in nbio_v6_1_sdma_doorbell_range()
138 …ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index… in nbio_v6_1_ih_doorbell_range()
A Dnbio_v7_4.c171 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); in nbio_v7_4_sdma_doorbell_range()
197 BIF_MMSCH0_DOORBELL_RANGE, OFFSET, in nbio_v7_4_vcn_doorbell_range()
239 …ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index… in nbio_v7_4_ih_doorbell_range()
A Dvega20_ih.c223 IH_DOORBELL_RPTR, OFFSET, in vega20_ih_doorbell_rptr()
290 val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, OFFSET, doorbell_index); in vega20_setup_retry_doorbell()
A Dtonga_ih.c148 OFFSET, adev->irq.ih.doorbell_index); in tonga_ih_irq_init()
/drivers/mtd/nand/raw/
A Dtegra_nand.c156 #define OFFSET(val, off) ((val) < (off) ? 0 : (val) - (off)) macro
794 reg |= TIMING_TCR_TAR_TRR(OFFSET(val, 3)); in tegra_nand_setup_timing()
799 reg |= TIMING_TCS(OFFSET(val, 2)); in tegra_nand_setup_timing()
803 reg |= TIMING_TRP(OFFSET(val, 1)) | TIMING_TRP_RESP(OFFSET(val, 1)); in tegra_nand_setup_timing()
805 reg |= TIMING_TWB(OFFSET(DIV_ROUND_UP(timings->tWB_max, period), 1)); in tegra_nand_setup_timing()
806 reg |= TIMING_TWHR(OFFSET(DIV_ROUND_UP(timings->tWHR_min, period), 1)); in tegra_nand_setup_timing()
807 reg |= TIMING_TWH(OFFSET(DIV_ROUND_UP(timings->tWH_min, period), 1)); in tegra_nand_setup_timing()
808 reg |= TIMING_TWP(OFFSET(DIV_ROUND_UP(timings->tWP_min, period), 1)); in tegra_nand_setup_timing()
809 reg |= TIMING_TRH(OFFSET(DIV_ROUND_UP(timings->tREH_min, period), 1)); in tegra_nand_setup_timing()
814 reg = TIMING_TADL(OFFSET(val, 3)); in tegra_nand_setup_timing()
/drivers/gpu/drm/nouveau/dispnv50/
A Dcore507d.c45 NVVAL(NV507D, SET_NOTIFIER_CONTROL, OFFSET, NV50_DISP_CORE_NTFY >> 2) | in core507d_update()
92 NVVAL(NV507D, SET_NOTIFIER_CONTROL, OFFSET, NV50_DISP_CORE_NTFY >> 2) | in core507d_read_caps()
A Dcorec37d.c63 NVVAL(NVC37D, SET_NOTIFIER_CONTROL, OFFSET, NV50_DISP_CORE_NTFY >> 4) | in corec37d_update()
/drivers/hwmon/
A Dadt7475.c32 OFFSET = 3, // Dup enumerator
425 case OFFSET: in temp_show()
476 case OFFSET: in temp_store()
479 out = data->temp[OFFSET][sattr->index] = val / 1000; in temp_store()
482 out = data->temp[OFFSET][sattr->index] = val / 500; in temp_store()
529 case OFFSET: in temp_store()
1128 static SENSOR_DEVICE_ATTR_2_RW(temp1_offset, temp, OFFSET, 0);
1138 static SENSOR_DEVICE_ATTR_2_RW(temp2_offset, temp, OFFSET, 1);
1149 static SENSOR_DEVICE_ATTR_2_RW(temp3_offset, temp, OFFSET, 2);
1454 data->temp[OFFSET][i] = ret; in adt7475_update_limits()
/drivers/media/dvb-frontends/
A Dbcm3510_priv.h180 u8 OFFSET :1; member
205 u8 OFFSET :1; member
/drivers/infiniband/hw/hfi1/
A Dtrace.c334 KDETH_GET(eh->tid_rdma.w_data.kdeth0, OFFSET), in parse_everbs_hdrs()
360 KDETH_GET(eh->tid_rdma.r_rsp.kdeth0, OFFSET), in parse_everbs_hdrs()
A Duser_sdma.c450 req->tidoffset = KDETH_GET(req->hdr.kdeth.ver_tid_offset, OFFSET) * in hfi1_user_sdma_process_request()
875 tidoff = KDETH_GET(kval, OFFSET) * in check_header_template()
1016 KDETH_SET(hdr->kdeth.ver_tid_offset, OFFSET, in set_txreq_header()

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