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Searched refs:OP (Results 1 – 17 of 17) sorted by relevance

/drivers/cpufreq/
A Dspeedstep-centrino.c101 OP(600, 844),
102 OP(800, 988),
103 OP(900, 1004),
110 OP(600, 844),
111 OP(800, 972),
112 OP(900, 988),
113 OP(1000, 1004),
120 OP( 600, 956),
121 OP( 800, 1020),
122 OP( 900, 1100),
[all …]
A Dpxa3xx-cpufreq.c72 #define OP(cpufreq, _xl, _xn, _hss, _dmc, _smc, _sfl, _dfi, vcore, vsram) \ macro
88 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
89 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
90 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
91 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
96 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
97 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
98 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
99 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
100 OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */
/drivers/infiniband/hw/hfi1/
A Duc.c11 #define OP(x) UC_OP(x) macro
176 case OP(SEND_FIRST): in hfi1_make_uc_req()
179 case OP(SEND_MIDDLE): in hfi1_make_uc_req()
299 case OP(SEND_FIRST): in hfi1_uc_rcv()
300 case OP(SEND_ONLY): in hfi1_uc_rcv()
316 case OP(SEND_FIRST): in hfi1_uc_rcv()
317 case OP(SEND_MIDDLE): in hfi1_uc_rcv()
348 case OP(SEND_FIRST): in hfi1_uc_rcv()
349 case OP(SEND_ONLY): in hfi1_uc_rcv()
372 case OP(SEND_MIDDLE): in hfi1_uc_rcv()
[all …]
A Dtrace.c285 case OP(RC, RDMA_WRITE_ONLY): in parse_everbs_hdrs()
286 case OP(UC, RDMA_WRITE_ONLY): in parse_everbs_hdrs()
295 case OP(RC, ACKNOWLEDGE): in parse_everbs_hdrs()
300 case OP(TID_RDMA, WRITE_REQ): in parse_everbs_hdrs()
339 case OP(TID_RDMA, READ_REQ): in parse_everbs_hdrs()
351 case OP(TID_RDMA, READ_RESP): in parse_everbs_hdrs()
371 case OP(TID_RDMA, ACK): in parse_everbs_hdrs()
387 case OP(TID_RDMA, RESYNC): in parse_everbs_hdrs()
402 case OP(RC, COMPARE_SWAP): in parse_everbs_hdrs()
403 case OP(RC, FETCH_ADD): in parse_everbs_hdrs()
[all …]
A Drc.c122 case OP(SEND_ONLY): in make_rc_ack()
123 case OP(ACKNOWLEDGE): in make_rc_ack()
908 case OP(SEND_FIRST): in hfi1_make_rc_req()
911 case OP(SEND_MIDDLE): in hfi1_make_rc_req()
2358 case OP(ACKNOWLEDGE): in rc_rcv_resp()
2617 case OP(FETCH_ADD): { in rc_rcv_error()
2816 case OP(SEND_FIRST): in hfi1_rc_rcv()
2817 case OP(SEND_MIDDLE): in hfi1_rc_rcv()
2855 case OP(SEND_FIRST): in hfi1_rc_rcv()
2889 case OP(SEND_ONLY): in hfi1_rc_rcv()
[all …]
A Drc.h11 #define OP(x) IB_OPCODE_RC_##x macro
22 qp->s_ack_state = OP(ACKNOWLEDGE); in update_ack_queue()
A Dtid_rdma.c2192 qp->s_ack_state = OP(ACKNOWLEDGE); in tid_rdma_rcv_error()
5480 e->opcode == OP(RDMA_READ_REQUEST)) && in hfi1_tid_rdma_ack_interlock()
/drivers/tee/optee/
A DKconfig2 # OP-TEE Trusted Execution Environment Configuration
4 tristate "OP-TEE"
9 This implements the OP-TEE Trusted Execution Environment (TEE)
13 bool "Load OP-TEE image as firmware"
17 This loads the BL32 image for OP-TEE as firmware when the driver is
/drivers/pinctrl/cirrus/
A Dpinctrl-lochnagar.c440 #define LN_FUNC(NAME, TYPE, OP) \ argument
441 { .name = NAME, .type = LN_FTYPE_##TYPE, .op = OP }
443 #define LN_FUNC_PIN(REV, ID, OP) \ argument
444 LN_FUNC(lochnagar##REV##_##ID##_pin.name, PIN, OP)
446 #define LN1_FUNC_PIN(ID, OP) LN_FUNC_PIN(1, ID, OP) argument
447 #define LN2_FUNC_PIN(ID, OP) LN_FUNC_PIN(2, ID, OP) argument
449 #define LN_FUNC_AIF(REV, ID, OP) \ argument
450 LN_FUNC(lochnagar##REV##_##ID##_aif.name, AIF, OP)
452 #define LN1_FUNC_AIF(ID, OP) LN_FUNC_AIF(1, ID, OP) argument
453 #define LN2_FUNC_AIF(ID, OP) LN_FUNC_AIF(2, ID, OP) argument
[all …]
/drivers/firmware/arm_scmi/transports/
A DKconfig66 tristate "SCMI transport based on OP-TEE service"
73 This enables the OP-TEE service based transport for SCMI.
76 transport based on OP-TEE SCMI service, answer Y.
/drivers/gpu/drm/i915/
A Di915_utils.h241 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \ argument
248 OP; \
/drivers/gpu/drm/v3d/
A Dv3d_drv.h495 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \ argument
502 OP; \
/drivers/gpu/drm/vc4/
A Dvc4_drv.h874 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \ argument
881 OP; \
/drivers/char/hw_random/
A DKconfig509 tristate "OP-TEE based Random Number Generator support"
513 This driver provides support for OP-TEE based Random Number
/drivers/nvmem/
A DKconfig360 Say y here to enable the accesses to STM32MP SoC OTPs by the OP-TEE
/drivers/rtc/
A DKconfig1348 tristate "OP-TEE based RTC driver"
1351 Select this to get support for OP-TEE based RTC control on SoCs where
/drivers/net/ethernet/qlogic/qed/
A Dqed_debug.c3032 SET_VAR_FIELD(cam_addr, VFC_CAM_ADDR, OP, VFC_OPCODE_CAM_RD); in qed_grc_dump_vfc_cam()
3079 SET_VAR_FIELD(ram_addr, VFC_RAM_ADDR, OP, VFC_OPCODE_RAM_RD); in qed_grc_dump_vfc_ram()

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