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Searched refs:OTG (Results 1 – 25 of 61) sorted by relevance

123

/drivers/gpu/drm/amd/display/dc/resource/dcn35/
A Ddcn35_resource.h174 SRII(PIXEL_RATE_CNTL, OTG, 0), \
175 SRII(PIXEL_RATE_CNTL, OTG, 1),\
176 SRII(PIXEL_RATE_CNTL, OTG, 2),\
177 SRII(PIXEL_RATE_CNTL, OTG, 3),\
228 SRI_ARR(OTG_H_TOTAL, OTG, inst),\
230 SRI_ARR(OTG_H_SYNC_A, OTG, inst),\
233 SRI_ARR(OTG_V_TOTAL, OTG, inst),\
235 SRI_ARR(OTG_V_SYNC_A, OTG, inst),\
237 SRI_ARR(OTG_CONTROL, OTG, inst),\
250 SRI_ARR(OTG_STATUS, OTG, inst),\
[all …]
/drivers/gpu/drm/amd/display/dc/optc/dcn314/
A Ddcn314_optc.h35 SRI(OTG_VREADY_PARAM, OTG, inst),\
42 SRI(OTG_H_TOTAL, OTG, inst),\
44 SRI(OTG_H_SYNC_A, OTG, inst),\
47 SRI(OTG_V_TOTAL, OTG, inst),\
49 SRI(OTG_V_SYNC_A, OTG, inst),\
51 SRI(OTG_CONTROL, OTG, inst),\
55 SRI(OTG_V_TOTAL_MAX, OTG, inst),\
58 SRI(OTG_TRIGA_CNTL, OTG, inst),\
62 SRI(OTG_STATUS, OTG, inst),\
80 SRI(OTG_CRC_CNTL, OTG, inst),\
[all …]
/drivers/gpu/drm/amd/display/dc/optc/dcn31/
A Ddcn31_optc.h34 SRI(OTG_VREADY_PARAM, OTG, inst),\
41 SRI(OTG_H_TOTAL, OTG, inst),\
43 SRI(OTG_H_SYNC_A, OTG, inst),\
46 SRI(OTG_V_TOTAL, OTG, inst),\
48 SRI(OTG_V_SYNC_A, OTG, inst),\
50 SRI(OTG_CONTROL, OTG, inst),\
57 SRI(OTG_TRIGA_CNTL, OTG, inst),\
61 SRI(OTG_STATUS, OTG, inst),\
79 SRI(OTG_CRC_CNTL, OTG, inst),\
100 SRI(OTG_CRC_CNTL2, OTG, inst),\
[all …]
/drivers/gpu/drm/amd/display/dc/optc/dcn30/
A Ddcn30_optc.h43 SRI(OTG_H_TOTAL, OTG, inst),\
45 SRI(OTG_H_SYNC_A, OTG, inst),\
48 SRI(OTG_V_TOTAL, OTG, inst),\
50 SRI(OTG_V_SYNC_A, OTG, inst),\
52 SRI(OTG_CONTROL, OTG, inst),\
60 SRI(OTG_TRIGA_CNTL, OTG, inst),\
64 SRI(OTG_STATUS, OTG, inst),\
84 SRI(OTG_CRC_CNTL, OTG, inst),\
85 SRI(OTG_CRC_CNTL2, OTG, inst),\
94 SRI(OTG_DRR_CONTROL, OTG, inst)
[all …]
/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_clock_source.h72 SRII(PIXEL_RATE_CNTL, OTG, 0),\
73 SRII(PIXEL_RATE_CNTL, OTG, 1),\
74 SRII(PIXEL_RATE_CNTL, OTG, 2),\
77 SRII(PIXEL_RATE_CNTL, OTG, 5)
86 SRII(PIXEL_RATE_CNTL, OTG, 1)
101 SRII(PIXEL_RATE_CNTL, OTG, 3)
116 SRII(PIXEL_RATE_CNTL, OTG, 3)
131 SRII(PIXEL_RATE_CNTL, OTG, 3)
149 SRII(PIXEL_RATE_CNTL, OTG, 4)
158 SRII(PIXEL_RATE_CNTL, OTG, 1)
[all …]
/drivers/gpu/drm/amd/display/dc/optc/dcn10/
A Ddcn10_optc.h37 SRI(OTG_VREADY_PARAM, OTG, inst),\
42 SRI(OTG_H_TOTAL, OTG, inst),\
44 SRI(OTG_H_SYNC_A, OTG, inst),\
47 SRI(OTG_V_TOTAL, OTG, inst),\
49 SRI(OTG_V_SYNC_A, OTG, inst),\
52 SRI(OTG_CONTROL, OTG, inst),\
56 SRI(OTG_V_TOTAL_MAX, OTG, inst),\
57 SRI(OTG_V_TOTAL_MID, OTG, inst),\
60 SRI(OTG_TRIGA_CNTL, OTG, inst),\
64 SRI(OTG_STATUS, OTG, inst),\
[all …]
/drivers/gpu/drm/amd/display/dc/dccg/dcn31/
A Ddcn31_dccg.h47 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
48 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
49 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
50 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
125 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 0, mask_sh),\
126 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 1, mask_sh),\
127 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 2, mask_sh),\
129 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
130 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
131 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
[all …]
/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
A Ddcn20_dccg.h81 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
82 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
83 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\
84 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh)
95 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
96 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
97 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 4, mask_sh),\
98 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 5, mask_sh),\
102 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 5, mask_sh)
110 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
[all …]
/drivers/gpu/drm/amd/display/dc/dccg/dcn32/
A Ddcn32_dccg.h80 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\
81 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\
82 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\
88 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
89 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
90 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
91 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\
92 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
93 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
94 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
[all …]
/drivers/gpu/drm/amd/display/dc/dccg/dcn314/
A Ddcn314_dccg.h52 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
53 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
54 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
55 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
119 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
120 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
121 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
123 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
124 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
125 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
[all …]
/drivers/gpu/drm/amd/display/dc/resource/dcn401/
A Ddcn401_resource.h479 SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst), \
480 SRI_ARR(OTG_VREADY_PARAM, OTG, inst), \
489 SRI_ARR(OTG_H_SYNC_A, OTG, inst), SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst), \
490 SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst), SRI_ARR(OTG_V_TOTAL, OTG, inst), \
492 SRI_ARR(OTG_V_SYNC_A, OTG, inst), SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst), \
493 SRI_ARR(OTG_CONTROL, OTG, inst), SRI_ARR(OTG_STEREO_CONTROL, OTG, inst), \
503 SRI_ARR(OTG_STATUS, OTG, inst), SRI_ARR(OTG_STATUS_POSITION, OTG, inst), \
518 SRI_ARR(OTG_GSL_CONTROL, OTG, inst), SRI_ARR(OTG_CRC_CNTL, OTG, inst), \
542 SRI_ARR(INTERRUPT_DEST, OTG, inst)
629 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0), DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1), \
[all …]
/drivers/gpu/drm/amd/display/dc/dccg/dcn35/
A Ddcn35_dccg.h110 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
111 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
112 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
114 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
115 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
116 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
117 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
127 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\
128 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh),\
129 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\
[all …]
/drivers/gpu/drm/amd/display/dc/dccg/dcn303/
A Ddcn303_dccg.h38 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
39 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1)
59 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
60 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
61 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\
62 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh)
/drivers/gpu/drm/amd/display/dc/resource/dcn36/
A Ddcn36_resource.h35 SRII(PIXEL_RATE_CNTL, OTG, 0), \
36 SRII(PIXEL_RATE_CNTL, OTG, 1),\
37 SRII(PIXEL_RATE_CNTL, OTG, 2),\
38 SRII(PIXEL_RATE_CNTL, OTG, 3),\
39 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
40 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
41 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
42 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
/drivers/gpu/drm/amd/display/dc/dccg/dcn401/
A Ddcn401_dccg.h77 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
78 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
79 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
81 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
82 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
83 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
84 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
108 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 0, mask_sh),\
109 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 1, mask_sh),\
110 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 2, mask_sh),\
[all …]
/drivers/gpu/drm/amd/display/dc/optc/dcn20/
A Ddcn20_optc.h33 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
34 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
35 SRI(OTG_GSL_WINDOW_X, OTG, inst),\
36 SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
37 SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
38 SRI(OTG_DSC_START_POSITION, OTG, inst),\
39 SRI(OTG_CRC_CNTL2, OTG, inst),\
45 SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst), \
46 SRI(OTG_DRR_CONTROL, OTG, inst),\
47 SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst)
/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource.h208 SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 0, index), \
211 SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 3, index)
1011 SRI_ARR(OTG_H_SYNC_A, OTG, inst), SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst), \
1012 SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst), SRI_ARR(OTG_V_TOTAL, OTG, inst), \
1014 SRI_ARR(OTG_V_SYNC_A, OTG, inst), SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst), \
1015 SRI_ARR(OTG_CONTROL, OTG, inst), SRI_ARR(OTG_STEREO_CONTROL, OTG, inst), \
1025 SRI_ARR(OTG_STATUS, OTG, inst), SRI_ARR(OTG_STATUS_POSITION, OTG, inst), \
1040 SRI_ARR(OTG_GSL_CONTROL, OTG, inst), SRI_ARR(OTG_CRC_CNTL, OTG, inst), \
1063 SRI_ARR(INTERRUPT_DEST, OTG, inst)
1244 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0), DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1), \
[all …]
/drivers/gpu/drm/amd/display/dc/optc/dcn201/
A Ddcn201_optc.h33 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
34 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
35 SRI(OTG_GSL_WINDOW_X, OTG, inst),\
36 SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
37 SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
38 SRI(OTG_DSC_START_POSITION, OTG, inst),\
/drivers/gpu/drm/amd/display/dc/hwss/dce/
A Ddce_hwseq.h373 HWSEQ_PIXEL_RATE_REG_LIST_201(OTG), \
374 HWSEQ_PHYPLL_REG_LIST_201(OTG), \
397 HWSEQ_PIXEL_RATE_REG_LIST_3(OTG), \
398 HWSEQ_PHYPLL_REG_LIST_3(OTG), \
428 SRII(PIXEL_RATE_CNTL, OTG, 0), \
429 SRII(PIXEL_RATE_CNTL, OTG, 1),\
430 SRII(PIXEL_RATE_CNTL, OTG, 2),\
431 SRII(PIXEL_RATE_CNTL, OTG, 3),\
538 HWSEQ_PIXEL_RATE_REG_LIST_302(OTG), \
539 HWSEQ_PHYPLL_REG_LIST_302(OTG), \
[all …]
/drivers/usb/phy/
A DKconfig19 Enable this to support the USB OTG transceiver in AB8500 chip.
24 tristate "Freescale USB OTG Transceiver Driver"
29 Enable this to support Freescale USB OTG transceiver.
68 Enable this to support the USB OTG transceiver on TWL6030
70 and OTG SRP events capabilities. For all other transceiver functionality
86 NOT support role switch. OTG devices that can do role switch
91 tristate "OMAP USB OTG controller driver"
94 Enable this to support some transceivers on OMAP1 platforms. OTG
124 and OTG drivers (to be selected separately).
154 Enable this to support ULPI connected USB OTG transceivers which
/drivers/gpu/drm/amd/display/dc/dccg/dcn30/
A Ddcn30_dccg.h35 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
36 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
37 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\
38 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5),\
/drivers/usb/core/
A DKconfig43 no more than 30 seconds (as required by the USB OTG spec).
60 bool "OTG support"
63 The most notable feature of USB OTG is support for a
73 bool "Rely on OTG and EH Targeted Peripherals List"
79 USB OTG and EH specification for all devices not on your product's
88 external hubs. OTG hosts are allowed to reduce hardware
90 are "Embedded Hosts" that don't offer OTG support.
93 tristate "USB 2.0 OTG FSM implementation"
97 Implements OTG Finite State Machine as specified in On-The-Go
/drivers/gpu/drm/amd/display/dc/irq/dcn401/
A Dirq_service_dcn401.c227 IRQ_REG_ENTRY(OTG, reg_num,\
237 IRQ_REG_ENTRY(OTG, reg_num,\
245 IRQ_REG_ENTRY(OTG, reg_num,\
252 IRQ_REG_ENTRY(OTG, reg_num,\
259 IRQ_REG_ENTRY(OTG, reg_num,\
/drivers/gpu/drm/amd/display/dc/irq/dcn32/
A Dirq_service_dcn32.c247 IRQ_REG_ENTRY(OTG, reg_num,\
257 IRQ_REG_ENTRY(OTG, reg_num,\
265 IRQ_REG_ENTRY(OTG, reg_num,\
272 IRQ_REG_ENTRY(OTG, reg_num,\
279 IRQ_REG_ENTRY(OTG, reg_num,\
/drivers/gpu/drm/amd/display/dc/irq/dcn201/
A Dirq_service_dcn201.c166 IRQ_REG_ENTRY(OTG, reg_num,\
177 IRQ_REG_ENTRY(OTG, reg_num,\
184 IRQ_REG_ENTRY(OTG, reg_num,\
192 IRQ_REG_ENTRY(OTG, reg_num,\

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