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Searched refs:OTG_MASTER (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
A Ddcn401_hwseq.c766 if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER)) in dcn401_enable_stream_timing()
835 resource_is_pipe_type(opp_heads[i], OTG_MASTER)); in dcn401_enable_stream_timing()
1580 resource_is_pipe_type(opp_heads[i], OTG_MASTER)); in dcn401_update_odm()
1684 if (!resource_is_pipe_type(pipe, OTG_MASTER) || in dcn401_interdependent_update_lock()
1696 if (!resource_is_pipe_type(pipe, OTG_MASTER) || in dcn401_interdependent_update_lock()
1717 if (!resource_is_pipe_type(pipe, OTG_MASTER) || in dcn401_interdependent_update_lock()
1965 if (resource_is_pipe_type(pipe_ctx, OTG_MASTER)) { in dcn401_program_pipe()
2184 if (resource_is_pipe_type(pipe, OTG_MASTER) && in dcn401_program_front_end_for_ctx()
2291 if (resource_is_pipe_type(old_pipe, OTG_MASTER) && resource_is_pipe_type(pipe, OTG_MASTER) && in dcn401_post_unlock_program_front_end()
2461 if (resource_is_pipe_type(new_pipe, OTG_MASTER) && in dcn401_detect_pipe_changes()
[all …]
/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
A Ddcn32_hwseq.c1155 resource_is_pipe_type(odm_pipe, OTG_MASTER)); in dcn32_update_odm()
1257 if (!resource_is_pipe_type(pipe, OTG_MASTER)) in dcn32_resync_fifo_dccg_dio()
1472 if (resource_is_pipe_type(phantom_pipe, OTG_MASTER)) { in dcn32_apply_update_flags_for_phantom()
1749 else if (resource_is_pipe_type(cur_pipe, OTG_MASTER)) { in dcn32_is_pipe_topology_transition_seamless()
1750 if (resource_is_pipe_type(new_pipe, OTG_MASTER)) in dcn32_is_pipe_topology_transition_seamless()
1827 if (!resource_is_pipe_type(pipe, OTG_MASTER) || in dcn32_interdependent_update_lock()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
A Ddcn20_clk_mgr.c160 if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER)) in dcn20_update_clocks_update_dentist()
191 if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER)) in dcn20_update_clocks_update_dentist()
/drivers/gpu/drm/amd/display/dc/core/
A Ddc_hw_sequencer.c800 if (resource_is_pipe_type(current_mpc_pipe, OTG_MASTER) && in hwss_build_fast_sequence()
1174 if (!resource_is_pipe_type(otg_master, OTG_MASTER) || in hwss_wait_for_odm_update_pending_complete()
1234 if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && dc->hwss.wait_for_all_pending_updates) { in hwss_wait_for_outstanding_hw_updates()
A Ddc_resource.c1851 if (resource_is_pipe_type(cur_pipe, OTG_MASTER) && in recource_find_free_pipe_used_as_otg_master_in_cur_res_ctx()
1932 case OTG_MASTER: in resource_is_pipe_type()
1955 resource_is_pipe_type(&res_ctx->pipe_ctx[i], OTG_MASTER)) in resource_get_otg_master_for_stream()
1971 if (!resource_is_pipe_type(otg_master, OTG_MASTER)) { in resource_get_opp_heads_for_otg_master()
2201 resource_is_pipe_type(opp_head, OTG_MASTER)); in resource_get_odm_slice_src_rect()
2263 if (!resource_is_pipe_type(otg_master_a, OTG_MASTER) || in resource_is_odm_topology_changed()
2264 !resource_is_pipe_type(otg_master_b, OTG_MASTER)) in resource_is_odm_topology_changed()
3200 if (resource_is_pipe_type(last_opp_head, OTG_MASTER)) in release_pipes_and_remove_odm_slice()
5261 if (!resource_is_pipe_type(pipe_ctx_old, OTG_MASTER)) in reset_syncd_pipes_from_disabled_pipes()
A Ddc.c2065 if (!resource_is_pipe_type(pipe, OTG_MASTER) || in determine_pipe_unlock_order()
2123 if (resource_is_pipe_type(pipe, OTG_MASTER)) { in dc_commit_state_no_check()
3566 if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && pipe_ctx->stream == stream) { in commit_planes_do_stream_update()
4889 if (resource_is_pipe_type(pipe, OTG_MASTER)) { in commit_minimal_transition_state()
/drivers/gpu/drm/amd/display/dc/inc/
A Dresource.h260 OTG_MASTER, enumerator
/drivers/gpu/drm/amd/display/dc/
A Ddc_dmub_srv.c482 if (!resource_is_pipe_type(pipe, OTG_MASTER)) in dc_dmub_srv_p_state_delegate()
671 if (!resource_is_pipe_type(pipe, OTG_MASTER) || in populate_subvp_cmd_vblank_pipe_info()
845 if (resource_is_pipe_type(phantom_pipe, OTG_MASTER) && in populate_subvp_cmd_pipe_info()
894 if (resource_is_pipe_type(pipe, OTG_MASTER) && in dc_dmub_setup_subvp_dmub_command()
913 if (resource_is_pipe_type(pipe, OTG_MASTER) && in dc_dmub_setup_subvp_dmub_command()
917 } else if (resource_is_pipe_type(pipe, OTG_MASTER) && in dc_dmub_setup_subvp_dmub_command()
/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
A Ddcn20_hwseq.c947 resource_is_pipe_type(opp_heads[i], OTG_MASTER)); in dcn20_enable_stream_timing()
1506 if (resource_is_pipe_type(new_pipe, OTG_MASTER) && in dcn20_detect_pipe_changes()
1563 if (resource_is_pipe_type(new_pipe, OTG_MASTER)) { in dcn20_detect_pipe_changes()
1850 if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && in dcn20_update_dchubp_dpp()
1927 if (resource_is_pipe_type(pipe_ctx, OTG_MASTER)) { in dcn20_program_pipe()
2144 if (resource_is_pipe_type(pipe, OTG_MASTER) && in dcn20_program_front_end_for_ctx()
2286 if (resource_is_pipe_type(old_pipe, OTG_MASTER) && resource_is_pipe_type(pipe, OTG_MASTER) && in dcn20_post_unlock_program_front_end()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
A Ddcn32_clk_mgr.c379 if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER)) in dcn32_update_clocks_update_dentist()
433 if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER)) in dcn32_update_clocks_update_dentist()
/drivers/gpu/drm/amd/display/dc/link/accessories/
A Dlink_dp_cts.c659 if (resource_is_pipe_type(&pipes[i], OTG_MASTER) && in dp_set_test_pattern()
/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddcn32_fpu.c823 if (!resource_is_pipe_type(pipe, OTG_MASTER) || in subvp_drr_schedulable()
839 if (!resource_is_pipe_type(drr_pipe, OTG_MASTER) || in subvp_drr_schedulable()
930 if (!resource_is_pipe_type(pipe, OTG_MASTER) || in subvp_vblank_schedulable()
1101 if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && in assign_subvp_index()
/drivers/gpu/drm/amd/display/dc/link/
A Dlink_dpms.c198 return resource_is_pipe_type(pipe, OTG_MASTER) && in is_master_pipe_for_link()
/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource.c1907 if (resource_is_pipe_type(pipe, OTG_MASTER)) in dcn32_populate_dml_pipes_from_context()

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