| /drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
| A D | dml2_core_shared_types.h | 284 double OutputBpp[DML2_MAX_PLANES]; member
520 double OutputBpp[DML2_MAX_PLANES]; member
803 double OutputBpp[DML2_MAX_PLANES]; member
1032 double OutputBpp[DML2_MAX_PLANES]; member
1141 double OutputBpp[DML2_MAX_PLANES]; member
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| A D | dml2_core_dcn4_calcs.c | 4456 double OutputBpp, in RequiredDTBCLK() argument
4479 double OutputBpp, in DSCDelayRequirement() argument
8426 s->OutputBpp[k], in dml_core_mode_support()
8440 &mode_lib->ms.OutputBpp[k], in dml_core_mode_support()
8445 if (s->OutputBpp[k] == 0.0) { in dml_core_mode_support()
8446 s->OutputBpp[k] = mode_lib->ms.OutputBpp[k]; in dml_core_mode_support()
8700 mode_lib->ms.OutputBpp[k], in dml_core_mode_support()
8800 s->OutputBpp[k], in dml_core_mode_support()
9560 mode_lib->ms.support.OutputBpp[k] = mode_lib->ms.OutputBpp[k]; in dml_core_mode_support()
10624 s->OutputBpp[k], in dml_core_mode_programming()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | display_mode_vba_util_32.h | 313 double OutputBpp,
323 double OutputBpp,
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| A D | display_mode_vba_util_32.c | 1691 double OutputBpp, in dml32_RequiredDTBCLK() argument
1705 return dml_max(PixelClock / 4.0 * OutputBpp / 24.0, 25.0); in dml32_RequiredDTBCLK()
1708 HCActive = dml_ceil(DSCSlices * dml_ceil(OutputBpp * in dml32_RequiredDTBCLK()
1720 double OutputBpp, in dml32_DSCDelayRequirement() argument
1732 if (DSCEnabled == true && OutputBpp != 0) { in dml32_DSCDelayRequirement()
1734 DSCDelayRequirement_val = 4 * (dml32_dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, in dml32_DSCDelayRequirement()
1738 DSCDelayRequirement_val = 2 * (dml32_dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, in dml32_DSCDelayRequirement()
1742 DSCDelayRequirement_val = dml32_dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, in dml32_DSCDelayRequirement()
1758 dml_print("DML::%s: OutputBpp = %f\n", __func__, OutputBpp); in dml32_DSCDelayRequirement()
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| A D | display_mode_vba_32.c | 3750 mode_lib->vba.OutputBpp[k] = mode_lib->vba.OutputBppPerState[mode_lib->vba.VoltageLevel][k]; in dml32_ModeSupportAndSystemConfigurationFull()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/ |
| A D | dml_top_types.h | 353 double OutputBpp[DML2_MAX_PLANES]; member
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| /drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | dml2_translation_helper.c | 842 out->OutputBpp[location] = (dml_float_t)output_bpc * 3; in populate_dml_output_cfg_from_stream_state()
846 out->OutputBpp[location] = (output_bpc * 3.0) / 2; in populate_dml_output_cfg_from_stream_state()
853 out->OutputBpp[location] = (dml_float_t)output_bpc * 2; in populate_dml_output_cfg_from_stream_state()
857 out->OutputBpp[location] = (dml_float_t)output_bpc * 3; in populate_dml_output_cfg_from_stream_state()
862 out->OutputBpp[location] = in->timing.dsc_cfg.bits_per_pixel / 16.0; in populate_dml_output_cfg_from_stream_state()
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| A D | dml2_utils.c | 123 dml_output_array->OutputBpp[dst_index] = dml_output_array->OutputBpp[src_index]; in dml2_util_copy_dml_output()
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| A D | display_mode_core_structs.h | 626 …dml_float_t OutputBpp[__DML_NUM_PLANES__]; //< brief Use by mode_programming to specify a output b… member
799 dml_float_t OutputBpp[__DML_NUM_PLANES__]; member
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| A D | display_mode_core.c | 446 dml_float_t OutputBpp,
738 dml_float_t OutputBpp,
4579 dml_float_t OutputBpp, in RequiredDTBCLK() argument
4587 return dml_max(PixelClock / 4.0 * OutputBpp / 24.0, 25.0); in RequiredDTBCLK()
4590 …dml_float_t HCActive = dml_ceil(DSCSlices * dml_ceil(OutputBpp * dml_ceil(HActive / DSCSlices, 1) … in RequiredDTBCLK()
5874 dml_float_t OutputBpp, in DSCDelayRequirement() argument
5885 if (DSCEnabled == true && OutputBpp != 0) { in DSCDelayRequirement()
5887 …DSCDelayRequirement_val = dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, (dml_uint_t)(dml_c… in DSCDelayRequirement()
5905 dml_print("DML::%s: OutputBpp = %f\n", __func__, OutputBpp); in DSCDelayRequirement()
8253 mode_lib->ms.support.OutputBpp[k] = mode_lib->ms.OutputBppPerState[k]; in dml_core_mode_support()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/ |
| A D | display_mode_vba.h | 507 double OutputBpp[DC__NUM_DPP__MAX]; member
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| A D | display_mode_vba.c | 627 mode_lib->vba.OutputBpp[mode_lib->vba.NumberOfActivePlanes] = in fetch_pipe_params()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | display_mode_vba_20.c | 1802 double bpp = mode_lib->vba.OutputBpp[k]; in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
5112 mode_lib->vba.OutputBpp[k] = in dml20_ModeSupportAndSystemConfigurationFull()
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| A D | display_mode_vba_20v2.c | 1838 double bpp = mode_lib->vba.OutputBpp[k]; in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
5228 mode_lib->vba.OutputBpp[k] = in dml20v2_ModeSupportAndSystemConfigurationFull()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| A D | display_mode_vba_21.c | 1794 double bpp = mode_lib->vba.OutputBpp[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
5234 mode_lib->vba.OutputBpp[k] = in dml21_ModeSupportAndSystemConfigurationFull()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | display_mode_vba_31.c | 2252 double BPP = v->OutputBpp[k];
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| /drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| A D | display_mode_vba_314.c | 2270 double BPP = v->OutputBpp[k];
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