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Searched refs:P (Results 1 – 25 of 79) sorted by relevance

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/drivers/pinctrl/sunplus/
A Dsppctl_sp7021.c65 P(0, 0), P(0, 1), P(0, 2), P(0, 3), P(0, 4), P(0, 5), P(0, 6), P(0, 7),
67 P(1, 0), P(1, 1), P(1, 2), P(1, 3), P(1, 4), P(1, 5), P(1, 6), P(1, 7),
68 P(2, 0), P(2, 1), P(2, 2), P(2, 3), P(2, 4), P(2, 5), P(2, 6), P(2, 7),
69 P(3, 0), P(3, 1), P(3, 2), P(3, 3), P(3, 4), P(3, 5), P(3, 6), P(3, 7),
70 P(4, 0), P(4, 1), P(4, 2), P(4, 3), P(4, 4), P(4, 5), P(4, 6), P(4, 7),
71 P(5, 0), P(5, 1), P(5, 2), P(5, 3), P(5, 4), P(5, 5), P(5, 6), P(5, 7),
72 P(6, 0), P(6, 1), P(6, 2), P(6, 3), P(6, 4), P(6, 5), P(6, 6), P(6, 7),
73 P(7, 0), P(7, 1), P(7, 2), P(7, 3), P(7, 4), P(7, 5), P(7, 6), P(7, 7),
74 P(8, 0), P(8, 1), P(8, 2), P(8, 3), P(8, 4), P(8, 5), P(8, 6), P(8, 7),
76 P(9, 0), P(9, 1), P(9, 2), P(9, 3), P(9, 4), P(9, 5), P(9, 6), P(9, 7),
[all …]
/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
A Dnv50.c58 int P, N, M, id; in read_pll_src() local
75 P = (coef & 0x00070000) >> 16; in read_pll_src()
83 P = (coef & 0x00070000) >> 16; in read_pll_src()
110 P += (coef & 0x00070000) >> 16; in read_pll_src()
119 return (ref * N / M) >> P; in read_pll_src()
198 u32 P = 0; in nv50_clk_read() local
252 return read_pll(clk, 0x004008) >> P; in nv50_clk_read()
256 P = (read_div(clk) & 0x00000700) >> 8; in nv50_clk_read()
273 return read_pll(clk, 0x004028) >> P; in nv50_clk_read()
274 return read_pll(clk, 0x004030) >> P; in nv50_clk_read()
[all …]
A Dpllgt215.c31 u32 freq, int *pN, int *pfN, int *pM, int *P) in gt215_pll_calc() argument
36 *P = info->vco1.max_freq / freq; in gt215_pll_calc()
37 if (*P > info->max_p) in gt215_pll_calc()
38 *P = info->max_p; in gt215_pll_calc()
39 if (*P < info->min_p) in gt215_pll_calc()
40 *P = info->min_p; in gt215_pll_calc()
49 u32 tmp = freq * *P * M; in gt215_pll_calc()
67 err = abs(freq - (info->refclk * N / M / *P)); in gt215_pll_calc()
86 return info->refclk * *pN / *pM / *P; in gt215_pll_calc()
A Dmcp77.c87 u32 P = 0; in mcp77_clk_read() local
107 P = (nvkm_rd32(device, 0x004028) & 0x00070000) >> 16; in mcp77_clk_read()
113 case 0x00000003: return read_pll(clk, 0x004028) >> P; in mcp77_clk_read()
130 P = (nvkm_rd32(device, 0x004020) & 0x00070000) >> 16; in mcp77_clk_read()
134 return nvkm_clk_read(&clk->base, nv_clk_src_href) >> P; in mcp77_clk_read()
137 case 0x00000020: return read_pll(clk, 0x004028) >> P; in mcp77_clk_read()
138 case 0x00000030: return read_pll(clk, 0x004020) >> P; in mcp77_clk_read()
144 P = (read_div(clk) & 0x00000700) >> 8; in mcp77_clk_read()
148 return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P; in mcp77_clk_read()
150 return 500000 >> P; in mcp77_clk_read()
[all …]
A Dpllnv04.c49 int M, N, thisP, P; in getMNP_single() local
73 P = 1 << maxP; in getMNP_single()
74 if ((clk * P) < minvco) { in getMNP_single()
84 P = 1 << thisP; in getMNP_single()
85 clkP = clk * P; in getMNP_single()
107 calcclk = ((N * crystal + P/2) / P + M/2) / M; in getMNP_single()
228 int *N1, int *M1, int *N2, int *M2, int *P) in nv04_pll_calc() argument
233 ret = getMNP_single(subdev, info, freq, N1, M1, P); in nv04_pll_calc()
239 ret = getMNP_double(subdev, info, freq, N1, M1, N2, M2, P); in nv04_pll_calc()
A Dgk104.c65 u32 P = (coef & 0x003f0000) >> 16; in read_pll() local
78 P = 1; in read_pll()
82 P = (coef & 0x10000000) ? 2 : 1; in read_pll()
98 if (P == 0) in read_pll()
99 P = 1; in read_pll()
102 return sclk / (M * P); in read_pll()
268 int N, M, P, ret; in calc_pll() local
278 ret = gt215_pll_calc(subdev, &limits, freq, &N, NULL, &M, &P); in calc_pll()
282 *coef = (P << 16) | (N << 8) | M; in calc_pll()
A Dnv04.c35 int N1, M1, N2, M2, P; in nv04_clk_pll_calc() local
36 int ret = nv04_pll_calc(&clock->subdev, info, clk, &N1, &M1, &N2, &M2, &P); in nv04_clk_pll_calc()
43 pv->log2P = P; in nv04_clk_pll_calc()
A Dgt215.c112 u32 sclk = 0, P = 1, N = 1, M = 1; in read_pll() local
120 P = (coef & 0x003f0000) >> 16; in read_pll()
126 P = 1; in read_pll()
134 MP = M * P; in read_pll()
241 int P, N, M, diff; in gt215_pll_info() local
263 ret = gt215_pll_calc(subdev, &limits, khz, &N, NULL, &M, &P); in gt215_pll_info()
265 info->pll = (P << 16) | (N << 8) | M; in gt215_pll_info()
A Dnv40.c44 int P = (ctrl & 0x00070000) >> 16; in read_pll_1() local
52 return khz >> P; in read_pll_1()
65 int P = (ctrl & 0x00070000) >> 16; in read_pll_2() local
78 return khz >> P; in read_pll_2()
A Dpll.h9 int *N1, int *M1, int *N2, int *M2, int *P);
11 int *N, int *fN, int *M, int *P);
A Dgf100.c64 u32 P = (coef & 0x003f0000) >> 16; in read_pll() local
76 P = 1; in read_pll()
94 return sclk * N / M / P; in read_pll()
255 int N, M, P, ret; in calc_pll() local
265 ret = gt215_pll_calc(subdev, &limits, freq, &N, NULL, &M, &P); in calc_pll()
269 *coef = (P << 16) | (N << 8) | M; in calc_pll()
/drivers/isdn/mISDN/
A Ddsp_blowfish.c369 u32 *P = dsp->bf_p; in dsp_bf_encrypt() local
417 yl ^= P[16]; in dsp_bf_encrypt()
418 yr ^= P[17]; in dsp_bf_encrypt()
461 u32 *P = dsp->bf_p; in dsp_bf_decrypt() local
515 yr ^= P[17]; in dsp_bf_decrypt()
516 yl ^= P[16]; in dsp_bf_decrypt()
580 yl ^= P[16]; in encrypt_block()
581 yr ^= P[17]; in encrypt_block()
624 P[i] = bf_pbox[i]; in dsp_bf_init()
633 P[i] = P[i] ^ temp; in dsp_bf_init()
[all …]
/drivers/gpu/drm/i915/display/
A Dintel_overlay.c1516 P(OBUF_0Y); in intel_overlay_snapshot_print()
1517 P(OBUF_1Y); in intel_overlay_snapshot_print()
1524 P(UV_VPH); in intel_overlay_snapshot_print()
1528 P(DWINSZ); in intel_overlay_snapshot_print()
1529 P(SWIDTH); in intel_overlay_snapshot_print()
1534 P(OCLRC0); in intel_overlay_snapshot_print()
1535 P(OCLRC1); in intel_overlay_snapshot_print()
1536 P(DCLRKV); in intel_overlay_snapshot_print()
1537 P(DCLRKM); in intel_overlay_snapshot_print()
1542 P(OCMD); in intel_overlay_snapshot_print()
[all …]
/drivers/video/fbdev/nvidia/
A Dnv_hw.c148 P = (pll >> 16) & 0x07; in nvGetClocks()
163 P = (pll >> 16) & 0x07; in nvGetClocks()
175 P = (pll >> 16) & 0x0F; in nvGetClocks()
772 unsigned M, N, P; in CalcVClock() local
786 for (P = 0; P <= 4; P++) { in CalcVClock()
787 Freq = VClk << P; in CalcVClock()
794 M) >> P; in CalcVClock()
818 unsigned M, N, P; in CalcVClock2Stage() local
826 for (P = 0; P <= 6; P++) { in CalcVClock2Stage()
827 Freq = VClk << P; in CalcVClock2Stage()
[all …]
/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
A Dnv50.c41 int N1, M1, N2, M2, P; in nv50_devinit_pll_set() local
50 ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P); in nv50_devinit_pll_set()
61 nvkm_mask(device, info.reg + 8, 0x7fff00ff, (P << 28) | in nv50_devinit_pll_set()
66 (P << 22) | in nv50_devinit_pll_set()
68 (P << 16)); in nv50_devinit_pll_set()
72 nvkm_mask(device, info.reg + 0, 0x00070000, (P << 16)); in nv50_devinit_pll_set()
A Dgv100.c35 int N, fN, M, P; in gv100_devinit_pll_set() local
42 ret = gt215_pll_calc(subdev, &info, freq, &N, &fN, &M, &P); in gv100_devinit_pll_set()
52 nvkm_wr32(device, 0x00ef04 + (head * 0x40), (P << 16) | in gv100_devinit_pll_set()
A Dga100.c36 int N, fN, M, P; in ga100_devinit_pll_set() local
43 ret = gt215_pll_calc(subdev, &info, freq, &N, &fN, &M, &P); in ga100_devinit_pll_set()
54 nvkm_wr32(device, 0x00ef04 + (head * 0x40), (P << 16) | M); in ga100_devinit_pll_set()
A Dtu102.c36 int N, fN, M, P; in tu102_devinit_pll_set() local
43 ret = gt215_pll_calc(subdev, &info, freq, &N, &fN, &M, &P); in tu102_devinit_pll_set()
53 nvkm_wr32(device, 0x00ef04 + (head * 0x40), (P << 16) | in tu102_devinit_pll_set()
A Dgf100.c37 int N, fN, M, P; in gf100_devinit_pll_set() local
44 ret = gt215_pll_calc(subdev, &info, freq, &N, &fN, &M, &P); in gf100_devinit_pll_set()
54 nvkm_wr32(device, info.reg + 0x04, (P << 16) | (N << 8) | M); in gf100_devinit_pll_set()
A Dgt215.c37 int N, fN, M, P; in gt215_devinit_pll_set() local
44 ret = gt215_pll_calc(subdev, &info, freq, &N, &fN, &M, &P); in gt215_devinit_pll_set()
53 (P << 16) | (M << 8) | N); in gt215_devinit_pll_set()
/drivers/gpu/drm/nouveau/dispnv04/i2c/
A Dch7006_mode.c164 __MODE(29500, 720, 576, 944, 625, P, P, 145.592111636, 1_1, 0x7, PAL_LIKE, 800, 600),
165 MODE(36000, 800, 600, 960, 750, P, P, 119.304647022, 5_6, 0x6, PAL_LIKE),
166 MODE(39000, 800, 600, 936, 836, P, P, 110.127366499, 3_4, 0x1, PAL_LIKE),
167 MODE(39273, 800, 600, 1040, 630, P, P, 145.816809399, 5_6, 0x4, NTSC_LIKE),
168 MODE(43636, 800, 600, 1040, 700, P, P, 131.235128487, 3_4, 0x2, NTSC_LIKE),
169 MODE(47832, 800, 600, 1064, 750, P, P, 119.723275165, 7_10, 0x1, NTSC_LIKE),
/drivers/regulator/
A Dmax77620-regulator.c734 RAIL_LDO(LDO2, ldo2, "in-ldo2", P, 800000, 3950000, 50000),
735 RAIL_LDO(LDO3, ldo3, "in-ldo3-5", P, 800000, 3950000, 50000),
736 RAIL_LDO(LDO4, ldo4, "in-ldo4-6", P, 800000, 1587500, 12500),
737 RAIL_LDO(LDO5, ldo5, "in-ldo3-5", P, 800000, 3950000, 50000),
738 RAIL_LDO(LDO6, ldo6, "in-ldo4-6", P, 800000, 3950000, 50000),
752 RAIL_LDO(LDO2, ldo2, "in-ldo2", P, 800000, 3950000, 50000),
753 RAIL_LDO(LDO3, ldo3, "in-ldo3-5", P, 800000, 3950000, 50000),
754 RAIL_LDO(LDO4, ldo4, "in-ldo4-6", P, 800000, 1587500, 12500),
755 RAIL_LDO(LDO5, ldo5, "in-ldo3-5", P, 800000, 3950000, 50000),
756 RAIL_LDO(LDO6, ldo6, "in-ldo4-6", P, 800000, 3950000, 50000),
[all …]
/drivers/net/ethernet/intel/ixgbe/
A Dixgbe_type.h2548 #define IXGBE_PVFTDH(P) (0x06010 + (0x40 * (P))) argument
2549 #define IXGBE_PVFTDT(P) (0x06018 + (0x40 * (P))) argument
2550 #define IXGBE_PVFTXDCTL(P) (0x06028 + (0x40 * (P))) argument
2551 #define IXGBE_PVFTDWBAL(P) (0x06038 + (0x40 * (P))) argument
2552 #define IXGBE_PVFTDWBAH(P) (0x0603C + (0x40 * (P))) argument
3773 #define IXGBE_KRM_LINK_S1(P) ((P) ? 0x8200 : 0x4200) argument
3774 #define IXGBE_KRM_LINK_CTRL_1(P) ((P) ? 0x820C : 0x420C) argument
3775 #define IXGBE_KRM_AN_CNTL_1(P) ((P) ? 0x822C : 0x422C) argument
3776 #define IXGBE_KRM_AN_CNTL_8(P) ((P) ? 0x8248 : 0x4248) argument
3777 #define IXGBE_KRM_SGMII_CTRL(P) ((P) ? 0x82A0 : 0x42A0) argument
[all …]
/drivers/video/fbdev/kyro/
A DSTG4000Ramdac.c30 u32 F = 0, R = 0, P = 0; in InitialiseRamdac() local
87 *pixelClock = ProgramClock(REF_CLOCK, *pixelClock, &F, &R, &P); in InitialiseRamdac()
93 tmp |= ((P) | ((F - 2) << 2) | ((R - 2) << 11)); in InitialiseRamdac()
/drivers/video/fbdev/riva/
A Driva_hw.c618 unsigned int M, N, P, pll, MClk; in nv3UpdateArbitrationSettings() local
622 MClk = (N * chip->CrystalFreqKHz / M) >> P; in nv3UpdateArbitrationSettings()
802 unsigned int M, N, P, pll, MClk, NVClk, cfg1; in nv4UpdateArbitrationSettings() local
806 MClk = (N * chip->CrystalFreqKHz / M) >> P; in nv4UpdateArbitrationSettings()
809 NVClk = (N * chip->CrystalFreqKHz / M) >> P; in nv4UpdateArbitrationSettings()
1055 MClk = (N * chip->CrystalFreqKHz / M) >> P; in nv10UpdateArbitrationSettings()
1097 unsigned int M, N, P, pll, MClk, NVClk; in nForceUpdateArbitrationSettings() local
1163 unsigned M, N, P; in CalcVClock() local
1181 for (P = 0; P <= highP; P ++) in CalcVClock()
1183 Freq = VClk << P; in CalcVClock()
[all …]

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