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Searched refs:PACKET3_PREAMBLE_CNTL (Results 1 – 20 of 20) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
A Dvid.h268 #define PACKET3_PREAMBLE_CNTL 0x4A macro
A Dcikd.h392 #define PACKET3_PREAMBLE_CNTL 0x4A macro
A Dsoc15d.h343 #define PACKET3_PREAMBLE_CNTL 0x4A macro
A Dsid.h516 #define PACKET3_PREAMBLE_CNTL 0x4A macro
A Dnvd.h394 #define PACKET3_PREAMBLE_CNTL 0x4A macro
A Damdgpu_gfx.c2286 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in amdgpu_gfx_csb_preamble_start()
2335 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in amdgpu_gfx_csb_preamble_end()
A Dgfx_v6_0.c2038 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v6_0_cp_gfx_start()
2053 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v6_0_cp_gfx_start()
A Dgfx_v7_0.c2487 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v7_0_cp_gfx_start()
2511 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v7_0_cp_gfx_start()
A Dgfx_v8_0.c4147 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_cp_gfx_start()
4173 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_cp_gfx_start()
A Dgfx_v11_0.c3608 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v11_0_cp_gfx_start()
3635 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v11_0_cp_gfx_start()
A Dgfx_v9_0.c3343 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v9_0_cp_gfx_start()
3364 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v9_0_cp_gfx_start()
A Dgfx_v10_0.c6385 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v10_0_cp_gfx_start()
6412 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v10_0_cp_gfx_start()
/drivers/gpu/drm/radeon/
A Dni.c1552 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start()
1558 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start()
A Dnid.h1261 #define PACKET3_PREAMBLE_CNTL 0x4A macro
A Dsid.h1775 #define PACKET3_PREAMBLE_CNTL 0x4A macro
A Dcikd.h1853 #define PACKET3_PREAMBLE_CNTL 0x4A macro
A Dsi.c3572 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in si_cp_start()
3578 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in si_cp_start()
5706 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in si_get_csb_buffer()
5748 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in si_get_csb_buffer()
A Devergreend.h1656 #define PACKET3_PREAMBLE_CNTL 0x4A macro
A Dcik.c3996 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cik_cp_gfx_start()
4006 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cik_cp_gfx_start()
6710 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cik_get_csb_buffer()
6757 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cik_get_csb_buffer()
A Devergreen.c3026 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in evergreen_cp_start()
3032 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in evergreen_cp_start()

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