Searched refs:PACKET3_SET_CONTEXT_REG_START (Results 1 – 19 of 19) sorted by relevance
| /drivers/gpu/drm/amd/amdgpu/ |
| A D | vid.h | 344 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 macro
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| A D | cikd.h | 468 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 macro
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| A D | soc15d.h | 432 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 macro
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| A D | sid.h | 527 #define PACKET3_SET_CONTEXT_REG_START 0x000a000 macro
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| A D | nvd.h | 517 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 macro
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| A D | gfx_v7_0.c | 2499 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); in gfx_v7_0_cp_gfx_start()
2507 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); in gfx_v7_0_cp_gfx_start()
3899 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); in gfx_v7_0_get_csb_buffer()
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| A D | gfx_v6_0.c | 2046 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); in gfx_v6_0_cp_gfx_start()
2872 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); in gfx_v6_0_get_csb_buffer()
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| A D | amdgpu_gfx.c | 2316 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START); in amdgpu_gfx_csb_data_parser()
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| A D | gfx_v8_0.c | 1237 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); in gfx_v8_0_get_csb_buffer()
4161 ext->reg_index - PACKET3_SET_CONTEXT_REG_START); in gfx_v8_0_cp_gfx_start()
4169 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); in gfx_v8_0_cp_gfx_start()
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| A D | gfx_v11_0.c | 867 …_offset = SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; in gfx_v11_0_get_csb_buffer()
3622 PACKET3_SET_CONTEXT_REG_START); in gfx_v11_0_cp_gfx_start()
3630 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; in gfx_v11_0_cp_gfx_start()
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| A D | gfx_v10_0.c | 4339 …g_offset = SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; in gfx_v10_0_get_csb_buffer()
6399 PACKET3_SET_CONTEXT_REG_START); in gfx_v10_0_cp_gfx_start()
6407 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; in gfx_v10_0_cp_gfx_start()
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| A D | gfx_v9_0.c | 3357 ext->reg_index - PACKET3_SET_CONTEXT_REG_START); in gfx_v9_0_cp_gfx_start()
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| /drivers/gpu/drm/radeon/ |
| A D | evergreen_cs.c | 2319 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START; in evergreen_packet3_check()
2321 if ((start_reg < PACKET3_SET_CONTEXT_REG_START) || in evergreen_packet3_check()
2630 allowed_reg_base -= PACKET3_SET_CONTEXT_REG_START; in evergreen_packet3_check()
3599 allowed_reg_base -= PACKET3_SET_CONTEXT_REG_START; in evergreen_vm_packet3_check()
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| A D | nid.h | 1273 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 macro
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| A D | sid.h | 1786 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 macro
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| A D | cikd.h | 1929 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 macro
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| A D | evergreend.h | 1669 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 macro
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| A D | si.c | 5728 buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); in si_get_csb_buffer()
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| A D | cik.c | 6732 buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); in cik_get_csb_buffer()
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Completed in 201 milliseconds