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Searched refs:PACKET3_SET_SH_REG_START (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
A Dvid.h348 #define PACKET3_SET_SH_REG_START 0x00002c00 macro
A Dcikd.h472 #define PACKET3_SET_SH_REG_START 0x00002c00 macro
A Dsoc15d.h436 #define PACKET3_SET_SH_REG_START 0x00002c00 macro
A Dsid.h532 #define PACKET3_SET_SH_REG_START 0x00002c00 macro
A Dnvd.h526 #define PACKET3_SET_SH_REG_START 0x00002c00 macro
A Dgfx_v9_4_2.c383 - PACKET3_SET_SH_REG_START; in gfx_v9_4_2_run_shader()
391 - PACKET3_SET_SH_REG_START; in gfx_v9_4_2_run_shader()
398 - PACKET3_SET_SH_REG_START; in gfx_v9_4_2_run_shader()
A Dgfx_v8_0.c1531 ib.ptr[ib.length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START; in gfx_v8_0_do_edc_gpr_workarounds()
1537 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START; in gfx_v8_0_do_edc_gpr_workarounds()
1557 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START; in gfx_v8_0_do_edc_gpr_workarounds()
1563 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START; in gfx_v8_0_do_edc_gpr_workarounds()
1583 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START; in gfx_v8_0_do_edc_gpr_workarounds()
1589 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START; in gfx_v8_0_do_edc_gpr_workarounds()
A Dgfx_v9_0.c4692 - PACKET3_SET_SH_REG_START; in gfx_v9_0_do_edc_gpr_workarounds()
4699 - PACKET3_SET_SH_REG_START; in gfx_v9_0_do_edc_gpr_workarounds()
4720 - PACKET3_SET_SH_REG_START; in gfx_v9_0_do_edc_gpr_workarounds()
4727 - PACKET3_SET_SH_REG_START; in gfx_v9_0_do_edc_gpr_workarounds()
4748 - PACKET3_SET_SH_REG_START; in gfx_v9_0_do_edc_gpr_workarounds()
4755 - PACKET3_SET_SH_REG_START; in gfx_v9_0_do_edc_gpr_workarounds()
/drivers/gpu/drm/radeon/
A Dsid.h1791 #define PACKET3_SET_SH_REG_START 0x0000b000 macro
A Dcikd.h1933 #define PACKET3_SET_SH_REG_START 0x0000b000 macro

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