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Searched refs:PACKET3_SET_UCONFIG_REG_START (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
A Dvid.h353 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 macro
A Dcikd.h477 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 macro
A Dsoc15d.h444 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 macro
A Dnvd.h536 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 macro
A Dgfx_v7_0.c2046 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START); in gfx_v7_0_ring_test_ring()
2314 ib.ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START; in gfx_v7_0_ring_test_ib()
A Dgfx_v9_0.c1208 amdgpu_ring_write(ring, scratch - PACKET3_SET_UCONFIG_REG_START); in gfx_v9_0_ring_test_ring()
3377 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START)); in gfx_v9_0_cp_gfx_start()
A Dgfx_v9_4_3.c435 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); in gfx_v9_4_3_ring_test_ring()
A Dgfx_v12_0.c473 PACKET3_SET_UCONFIG_REG_START); in gfx_v12_0_ring_test_ring()
A Dgfx_v8_0.c851 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START); in gfx_v8_0_ring_test_ring()
A Dgfx_v11_0.c579 PACKET3_SET_UCONFIG_REG_START); in gfx_v11_0_ring_test_ring()
A Dgfx_v10_0.c4051 PACKET3_SET_UCONFIG_REG_START); in gfx_v10_0_ring_test_ring()
/drivers/gpu/drm/radeon/
A Dcikd.h1938 #define PACKET3_SET_UCONFIG_REG_START 0x00030000 macro
A Dcik.c3465 radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2)); in cik_ring_test()
3737 PACKET3_SET_UCONFIG_REG_START) >> 2)); in cik_ring_ib_execute()
3790 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2); in cik_ib_test()

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