Searched refs:PFIT_CONTROL (Results 1 – 14 of 14) sorted by relevance
| /drivers/gpu/drm/gma500/ |
| A D | oaktrail_lvds.c | 132 REG_WRITE(PFIT_CONTROL, 0); in oaktrail_lvds_mode_set()
138 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE); in oaktrail_lvds_mode_set()
142 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE | in oaktrail_lvds_mode_set()
145 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE | in oaktrail_lvds_mode_set()
148 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE); in oaktrail_lvds_mode_set()
150 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE); in oaktrail_lvds_mode_set()
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| A D | psb_intel_lvds.c | 268 lvds_priv->savePFIT_CONTROL = REG_READ(PFIT_CONTROL); in psb_intel_lvds_save()
309 REG_WRITE(PFIT_CONTROL, lvds_priv->savePFIT_CONTROL); in psb_intel_lvds_restore()
485 REG_WRITE(PFIT_CONTROL, pfit_control); in psb_intel_lvds_mode_set()
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| A D | oaktrail_device.c | 181 regs->psb.savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL); in oaktrail_save_display_registers()
305 PSB_WVDC32(regs->psb.savePFIT_CONTROL, PFIT_CONTROL); in oaktrail_restore_display_registers()
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| A D | psb_intel_display.c | 84 pfit_control = REG_READ(PFIT_CONTROL); in psb_intel_panel_fitter_pipe()
214 REG_WRITE(PFIT_CONTROL, 0); in psb_intel_crtc_mode_set()
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| A D | cdv_device.c | 259 regs->cdv.savePFIT_CONTROL = REG_READ(PFIT_CONTROL); in cdv_save_display_registers()
330 REG_WRITE(PFIT_CONTROL, regs->cdv.savePFIT_CONTROL); in cdv_restore_display_registers()
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| A D | oaktrail_crtc.c | 351 pfit_control = REG_READ(PFIT_CONTROL); in oaktrail_panel_fitter_pipe()
427 REG_WRITE(PFIT_CONTROL, 0); in oaktrail_crtc_mode_set()
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| A D | cdv_intel_display.c | 563 pfit_control = REG_READ(PFIT_CONTROL); in cdv_intel_panel_fitter_pipe()
762 REG_WRITE(PFIT_CONTROL, 0); in cdv_intel_crtc_mode_set()
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| A D | cdv_intel_lvds.c | 293 REG_WRITE(PFIT_CONTROL, pfit_control); in cdv_intel_lvds_mode_set()
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| A D | psb_intel_reg.h | 205 #define PFIT_CONTROL 0x61230 macro
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| A D | cdv_intel_dp.c | 1098 REG_WRITE(PFIT_CONTROL, pfit_control); in cdv_intel_dp_mode_set()
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| /drivers/gpu/drm/i915/display/ |
| A D | intel_pfit.c | 656 intel_de_read(display, PFIT_CONTROL(display)) & PFIT_ENABLE); in i9xx_pfit_enable()
661 intel_de_write(display, PFIT_CONTROL(display), in i9xx_pfit_enable()
681 intel_de_read(display, PFIT_CONTROL(display))); in i9xx_pfit_disable()
682 intel_de_write(display, PFIT_CONTROL(display), 0); in i9xx_pfit_disable()
704 tmp = intel_de_read(display, PFIT_CONTROL(display)); in i9xx_pfit_get_config()
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| A D | intel_pfit_regs.h | 10 #define PFIT_CONTROL(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230) macro
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| A D | intel_lvds.c | 148 tmp = intel_de_read(display, PFIT_CONTROL(display)); in intel_lvds_get_config()
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| A D | intel_overlay.c | 963 if (intel_de_read(display, PFIT_CONTROL(display)) & PFIT_VERT_AUTO_SCALE) in update_pfit_vscale_ratio()
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Completed in 34 milliseconds