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Searched refs:PFIT_PGM_RATIOS (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/i915/display/
A Dintel_pfit_regs.h31 #define PFIT_PGM_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) macro
A Dintel_pfit.c659 intel_de_write(display, PFIT_PGM_RATIOS(display), in i9xx_pfit_enable()
719 intel_de_read(display, PFIT_PGM_RATIOS(display)); in i9xx_pfit_get_config()
A Dintel_overlay.c956 u32 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display)); in update_pfit_vscale_ratio()
966 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display)); in update_pfit_vscale_ratio()
/drivers/gpu/drm/gma500/
A Doaktrail_device.c176 regs->psb.savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS); in oaktrail_save_display_registers()
306 PSB_WVDC32(regs->psb.savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS); in oaktrail_restore_display_registers()
A Dcdv_device.c254 regs->cdv.savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS); in cdv_save_display_registers()
331 REG_WRITE(PFIT_PGM_RATIOS, regs->cdv.savePFIT_PGM_RATIOS); in cdv_restore_display_registers()
A Dpsb_intel_lvds.c269 lvds_priv->savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS); in psb_intel_lvds_save()
310 REG_WRITE(PFIT_PGM_RATIOS, lvds_priv->savePFIT_PGM_RATIOS); in psb_intel_lvds_restore()
A Dpsb_intel_reg.h221 #define PFIT_PGM_RATIOS 0x61234 macro

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