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Searched refs:PG_DPP (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/display/dc/hwss/dcn351/
A Ddcn351_hwseq.c47 !update_state->pg_pipe_res_update[PG_DPP][i]) { in dcn351_calc_blocks_to_gate()
50 update_state->pg_pipe_res_update[PG_DPP][j] = false; in dcn351_calc_blocks_to_gate()
67 update_state->pg_pipe_res_update[PG_DPP][i]) { in dcn351_calc_blocks_to_ungate()
70 update_state->pg_pipe_res_update[PG_DPP][j] = true; in dcn351_calc_blocks_to_ungate()
115 update_state->pg_pipe_res_update[PG_DPP][i]) { in dcn351_hw_block_power_down()
172 update_state->pg_pipe_res_update[PG_DPP][i]) { in dcn351_hw_block_power_up()
/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
A Ddcn35_hwseq.c1095 !update_state->pg_pipe_res_update[PG_DPP][i]) { in dcn35_calc_blocks_to_gate()
1098 update_state->pg_pipe_res_update[PG_DPP][j] = false; in dcn35_calc_blocks_to_gate()
1131 if (j == PG_DPP && new_pipe->plane_res.dpp) in dcn35_calc_blocks_to_ungate()
1158 if (j == PG_DPP && in dcn35_calc_blocks_to_ungate()
1226 update_state->pg_pipe_res_update[PG_DPP][i]) { in dcn35_calc_blocks_to_ungate()
1229 update_state->pg_pipe_res_update[PG_DPP][j] = true; in dcn35_calc_blocks_to_ungate()
1280 update_state->pg_pipe_res_update[PG_DPP][i]) { in dcn35_hw_block_power_down()
1300 update_state->pg_pipe_res_update[PG_DPP][i]) { in dcn35_hw_block_power_down()
1363 update_state->pg_pipe_res_update[PG_DPP][i]) { in dcn35_hw_block_power_up()
1392 update_state->pg_pipe_res_update[PG_DPP][i]) { in dcn35_root_clock_control()
[all …]
/drivers/gpu/drm/amd/display/dc/pg/dcn35/
A Ddcn35_pg_cntl.c243 pg_cntl->pg_pipe_res_enable[PG_DPP][hubp_dpp_inst] = power_on; in pg_cntl35_hubp_dpp_pg_control()
489 pg_cntl->pg_pipe_res_enable[PG_DPP][i] = block_enabled; in pg_cntl35_init_pg_status()
/drivers/gpu/drm/amd/display/dc/
A Ddc.h805 PG_DPP, enumerator

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