| /drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_clock_source.h | 60 SRII(PHASE, DP_DTO, 0),\
61 SRII(PHASE, DP_DTO, 1),\
62 SRII(PHASE, DP_DTO, 2),\
63 SRII(PHASE, DP_DTO, 3),\
64 SRII(PHASE, DP_DTO, 4),\
65 SRII(PHASE, DP_DTO, 5),\
81 SRII(PHASE, DP_DTO, 0),\
82 SRII(PHASE, DP_DTO, 1),\
90 SRII(PHASE, DP_DTO, 0),\
91 SRII(PHASE, DP_DTO, 1),\
[all …]
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| A D | dce_clock_source.c | 989 REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor); in dcn31_program_pix_clk()
993 REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100); in dcn31_program_pix_clk()
1203 clock_hz = REG_READ(PHASE[inst]); in get_pixel_clk_frequency_100hz()
1313 REG_WRITE(PHASE[inst], pixel_clk); in dcn20_override_dp_pix_clk()
1343 REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor); in dcn3_program_pix_clk()
1347 REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100); in dcn3_program_pix_clk()
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| /drivers/gpu/drm/amd/display/dc/dccg/dcn31/ |
| A D | dcn31_dccg.h | 55 DCCG_SRII(PHASE, DTBCLK_DTO, 0),\
56 DCCG_SRII(PHASE, DTBCLK_DTO, 1),\
57 DCCG_SRII(PHASE, DTBCLK_DTO, 2),\
58 DCCG_SRII(PHASE, DTBCLK_DTO, 3),\
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| /drivers/gpu/drm/amd/display/dc/dccg/dcn314/ |
| A D | dcn314_dccg.h | 60 DCCG_SRII(PHASE, DTBCLK_DTO, 0),\
61 DCCG_SRII(PHASE, DTBCLK_DTO, 1),\
62 DCCG_SRII(PHASE, DTBCLK_DTO, 2),\
63 DCCG_SRII(PHASE, DTBCLK_DTO, 3),\
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.h | 200 SRII_ARR_2(PHASE, DP_DTO, 0, index), \
201 SRII_ARR_2(PHASE, DP_DTO, 1, index), \
202 SRII_ARR_2(PHASE, DP_DTO, 2, index), \
203 SRII_ARR_2(PHASE, DP_DTO, 3, index), \
1248 DCCG_SRII(PHASE, DTBCLK_DTO, 0), DCCG_SRII(PHASE, DTBCLK_DTO, 1), \
1249 DCCG_SRII(PHASE, DTBCLK_DTO, 2), DCCG_SRII(PHASE, DTBCLK_DTO, 3), \
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| /drivers/gpu/drm/nouveau/dispnv50/ |
| A D | head917d.c | 44 NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, PHASE, 0)); in head917d_dither()
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| A D | headca7d.c | 105 NVVAL(NVCA7D, HEAD_SET_DITHER_CONTROL, PHASE, 0)); in headca7d_dither()
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| A D | headc37d.c | 100 NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, PHASE, 0)); in headc37d_dither()
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| A D | head507d.c | 62 NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, PHASE, 0)); in head507d_dither()
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| A D | head907d.c | 91 NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, PHASE, 0)); in head907d_dither()
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| /drivers/scsi/ |
| A D | FlashPoint.c | 499 #define PHASE BIT(13) macro
1833 (PROG_HLT | RSEL | PHASE | BUS_FREE)); in FlashPoint_HandleInterrupt()
1869 (PHASE | IUNKWN | PROG_HLT)); in FlashPoint_HandleInterrupt()
2644 WRW_HARPOON((port + hp_intstat), PHASE); in FPT_sres()
2649 WRW_HARPOON((port + hp_intstat), PHASE); in FPT_sres()
2722 (PHASE | RESET)) in FPT_sres()
2814 WRW_HARPOON((port + hp_intstat), PHASE); in FPT_SendMsg()
2819 WRW_HARPOON((port + hp_intstat), PHASE); in FPT_SendMsg()
2822 (BUS_FREE | PHASE | XFER_CNT_0)); in FPT_SendMsg()
2838 (BUS_FREE | PHASE))) { in FPT_SendMsg()
[all …]
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| /drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| A D | dcn401_resource.h | 636 DCCG_SRII(PHASE, DP_DTO, 0), DCCG_SRII(PHASE, DP_DTO, 1), \
637 DCCG_SRII(PHASE, DP_DTO, 2), DCCG_SRII(PHASE, DP_DTO, 3), \
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