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Searched refs:PHYCLKPerState (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddisplay_mode_vba_util_32.h250 double PHYCLKPerState,
A Ddisplay_mode_vba_util_32.c1337 double PHYCLKPerState, in dml32_CalculateOutputLink() argument
1378 *OutBpp = dml32_TruncToValidBPP(dml_min(600, PHYCLKPerState) * 10, 3, HTotal, HActive, in dml32_CalculateOutputLink()
1472 PHYCLKPerState >= 270) { in dml32_CalculateOutputLink()
1478 if (*OutBpp == 0 && PHYCLKPerState < 540 && DSCEnable == true && in dml32_CalculateOutputLink()
1496 *OutBpp == 0 && PHYCLKPerState >= 540) { in dml32_CalculateOutputLink()
1503 if (*OutBpp == 0 && PHYCLKPerState < 810 && DSCEnable == true && in dml32_CalculateOutputLink()
1521 …= dm_dp_rate_na || OutputLinkDPRate == dm_dp_rate_hbr3) && *OutBpp == 0 && PHYCLKPerState >= 810) { in dml32_CalculateOutputLink()
A Ddisplay_mode_vba_32.c2088 mode_lib->vba.PHYCLKPerState[i], in dml32_ModeSupportAndSystemConfigurationFull()
/drivers/gpu/drm/amd/display/dc/dml/
A Ddisplay_mode_vba.h603 double PHYCLKPerState[DC__VOLTAGE_STATES]; member
A Ddisplay_mode_vba.c398 mode_lib->vba.PHYCLKPerState[i] = soc->clock_limits[i].phyclk_mhz; in fetch_socbb_params()
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddisplay_mode_vba_20.c4057 dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24, in dml20_ModeSupportAndSystemConfigurationFull()
4070 if (mode_lib->vba.PHYCLKPerState[i] >= 270.0) { in dml20_ModeSupportAndSystemConfigurationFull()
4099 if (mode_lib->vba.Outbpp == BPP_INVALID && mode_lib->vba.PHYCLKPerState[i] >= 540.0) { in dml20_ModeSupportAndSystemConfigurationFull()
4129 && mode_lib->vba.PHYCLKPerState[i] in dml20_ModeSupportAndSystemConfigurationFull()
A Ddisplay_mode_vba_20v2.c4171 dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24, in dml20v2_ModeSupportAndSystemConfigurationFull()
4185 if (mode_lib->vba.PHYCLKPerState[i] >= 270.0) { in dml20v2_ModeSupportAndSystemConfigurationFull()
4216 if (mode_lib->vba.Outbpp == BPP_INVALID && mode_lib->vba.PHYCLKPerState[i] >= 540.0) { in dml20v2_ModeSupportAndSystemConfigurationFull()
4248 && mode_lib->vba.PHYCLKPerState[i] in dml20v2_ModeSupportAndSystemConfigurationFull()
/drivers/gpu/drm/amd/display/dc/dml/dcn21/
A Ddisplay_mode_vba_21.c4265 dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24, in dml21_ModeSupportAndSystemConfigurationFull()
4279 if (mode_lib->vba.PHYCLKPerState[i] >= 270.0) { in dml21_ModeSupportAndSystemConfigurationFull()
4310 if (mode_lib->vba.Outbpp == BPP_INVALID && mode_lib->vba.PHYCLKPerState[i] >= 540.0) { in dml21_ModeSupportAndSystemConfigurationFull()
4342 && mode_lib->vba.PHYCLKPerState[i] in dml21_ModeSupportAndSystemConfigurationFull()
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddisplay_mode_vba_30.c4051 dml_min(600.0, v->PHYCLKPerState[i]) * 10, in dml30_ModeSupportAndSystemConfigurationFull()
4081 if (v->PHYCLKPerState[i] >= 270.0) { in dml30_ModeSupportAndSystemConfigurationFull()
4101 if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 540.0) { in dml30_ModeSupportAndSystemConfigurationFull()
4121 if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 810.0) { in dml30_ModeSupportAndSystemConfigurationFull()
/drivers/gpu/drm/amd/display/dc/dml2/
A Ddisplay_mode_core.c75 dml_float_t PHYCLKPerState,
5342 dml_float_t PHYCLKPerState, in CalculateOutputLink() argument
5384 …*OutBpp = TruncToValidBPP(dml_min(600, PHYCLKPerState) * 10, 3, HTotal, HActive, PixelClockBackEnd… in CalculateOutputLink()
5451 …putLinkDPRate == dml_dp_rate_na || OutputLinkDPRate == dml_dp_rate_hbr) && PHYCLKPerState >= 270) { in CalculateOutputLink()
5454 …if (*OutBpp == 0 && PHYCLKPerState < 540 && DSCEnable == dml_dsc_enable_if_necessary && ForcedOutp… in CalculateOutputLink()
5467 …dml_dp_rate_na || OutputLinkDPRate == dml_dp_rate_hbr2) && *OutBpp == 0 && PHYCLKPerState >= 540) { in CalculateOutputLink()
5471 …if (*OutBpp == 0 && PHYCLKPerState < 810 && DSCEnable == dml_dsc_enable_if_necessary && ForcedOutp… in CalculateOutputLink()
5484 …_rate_na || OutputLinkDPRate == dml_dp_rate_hbr3) && *OutBpp == 0 && PHYCLKPerState >= 810) { // V… in CalculateOutputLink()
/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddisplay_mode_vba_31.c4295 dml_min(600.0, v->PHYCLKPerState[i]) * 10,
4456 if (v->PHYCLKPerState[i] >= 270.0) {
4476 if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 540.0) {
4496 if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 810.0) {
/drivers/gpu/drm/amd/display/dc/dml/dcn314/
A Ddisplay_mode_vba_314.c4382 dml_min(600.0, v->PHYCLKPerState[i]) * 10,
4543 if (v->PHYCLKPerState[i] >= 270.0) {
4563 if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 540.0) {
4583 if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 810.0) {

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