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Searched refs:PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE_MASK (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/display/dc/resource/dcn31/
A Ddcn31_resource.h91 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE_MASK 0x00000100L macro
/drivers/gpu/drm/amd/include/asic_reg/dce/
A Ddce_11_2_sh_mask.h1707 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE_MASK 0x100 macro
A Ddce_12_0_sh_mask.h2788 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE_MASK macro
/drivers/gpu/drm/amd/include/asic_reg/dcn/
A Ddcn_1_0_sh_mask.h2141 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE_MASK macro
A Ddcn_3_1_6_sh_mask.h1470 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE_MASK macro
A Ddcn_3_0_0_sh_mask.h696 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE_MASK macro
A Ddcn_2_0_0_sh_mask.h705 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE_MASK macro
A Ddcn_4_1_0_sh_mask.h476 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE_MASK macro

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