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Searched refs:PHY_REG (Results 1 – 12 of 12) sorted by relevance

/drivers/net/ethernet/intel/e1000e/
A Dich8lan.h121 #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
122 #define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
123 #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
124 #define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
140 #define HV_MUX_DATA_CTRL PHY_REG(776, 16)
166 #define CV_SMB_CTRL PHY_REG(769, 23)
184 #define HV_SMB_ADDR PHY_REG(768, 26)
200 #define HV_OEM_BITS PHY_REG(768, 25)
215 #define HV_PM_CTRL PHY_REG(770, 17)
274 #define I217_CGFREG PHY_REG(772, 29)
[all …]
A Dethtool.c1351 e1e_rphy(hw, PHY_REG(2, 21), &phy_reg); in e1000_integrated_phy_loopback()
1354 e1e_wphy(hw, PHY_REG(2, 21), phy_reg); in e1000_integrated_phy_loopback()
1359 e1e_rphy(hw, PHY_REG(769, 16), &phy_reg); in e1000_integrated_phy_loopback()
1360 e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x000C); in e1000_integrated_phy_loopback()
1362 e1e_rphy(hw, PHY_REG(776, 16), &phy_reg); in e1000_integrated_phy_loopback()
1365 e1e_rphy(hw, PHY_REG(769, 16), &phy_reg); in e1000_integrated_phy_loopback()
1368 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); in e1000_integrated_phy_loopback()
1384 e1e_rphy(hw, PHY_REG(0, 21), &phy_reg); in e1000_integrated_phy_loopback()
1385 e1e_wphy(hw, PHY_REG(0, 21), phy_reg & ~BIT(3)); in e1000_integrated_phy_loopback()
1387 e1e_rphy(hw, PHY_REG(776, 18), &phy_reg); in e1000_integrated_phy_loopback()
[all …]
A Dich8lan.c1619 PHY_REG(776, 20), in e1000_check_for_copper_link_ich8lan()
1632 PHY_REG(776, 20), in e1000_check_for_copper_link_ich8lan()
1644 PHY_REG(776, 20), in e1000_check_for_copper_link_ich8lan()
2706 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); in e1000_lv_jumbo_workaround_ich8lan()
2770 e1e_rphy(hw, PHY_REG(769, 23), &data); in e1000_lv_jumbo_workaround_ich8lan()
2773 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); in e1000_lv_jumbo_workaround_ich8lan()
2776 e1e_rphy(hw, PHY_REG(769, 16), &data); in e1000_lv_jumbo_workaround_ich8lan()
2781 e1e_rphy(hw, PHY_REG(776, 20), &data); in e1000_lv_jumbo_workaround_ich8lan()
2828 e1e_rphy(hw, PHY_REG(769, 23), &data); in e1000_lv_jumbo_workaround_ich8lan()
2833 e1e_rphy(hw, PHY_REG(769, 16), &data); in e1000_lv_jumbo_workaround_ich8lan()
[all …]
A Dregs.h243 #define I82579_DFT_CTRL PHY_REG(769, 20)
A Dnetdev.c3074 e1e_rphy(hw, PHY_REG(770, 26), &phy_data); in e1000_setup_rctl()
3077 e1e_wphy(hw, PHY_REG(770, 26), phy_data); in e1000_setup_rctl()
/drivers/phy/freescale/
A Dphy-fsl-samsung-hdmi.c287 { PHY_REG(8), 0x4f }, { PHY_REG(9), 0x30 },
288 { PHY_REG(10), 0x33 }, { PHY_REG(11), 0x65 },
292 { PHY_REG(15), 0x80 }, { PHY_REG(16), 0x6c },
293 { PHY_REG(17), 0xf2 }, { PHY_REG(18), 0x67 },
294 { PHY_REG(19), 0x00 }, { PHY_REG(20), 0x10 },
296 { PHY_REG(22), 0x30 }, { PHY_REG(23), 0x32 },
297 { PHY_REG(24), 0x60 }, { PHY_REG(25), 0x8f },
298 { PHY_REG(26), 0x00 }, { PHY_REG(27), 0x00 },
299 { PHY_REG(28), 0x08 }, { PHY_REG(29), 0x00 },
300 { PHY_REG(30), 0x00 }, { PHY_REG(31), 0x00 },
[all …]
/drivers/phy/rockchip/
A Dphy-rockchip-dphy-rx0.c109 #define PHY_REG(_offset, _width, _shift) \ macro
113 [GRF_DPHY_RX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON9, 4, 0),
116 [GRF_DPHY_RX0_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 0),
124 [GRF_DPHY_TX1RX1_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 0),
129 [GRF_DPHY_RX1_SRC_SEL] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 4),
130 [GRF_DPHY_TX1RX1_BASEDIR] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 5),
133 [GRF_DPHY_RX0_TESTDIN] = PHY_REG(RK3399_GRF_SOC_CON25, 8, 0),
134 [GRF_DPHY_RX0_TESTEN] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 8),
135 [GRF_DPHY_RX0_TESTCLK] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 9),
136 [GRF_DPHY_RX0_TESTCLR] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 10),
[all …]
A Dphy-rockchip-inno-csidphy.c92 #define PHY_REG(_offset, _width, _shift) \ macro
96 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 0),
97 [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 1, 8),
98 [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 4),
102 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 4, 0),
103 [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 1, 8),
104 [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 4, 4),
108 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 4, 8),
112 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3568_GRF_VI_CON0, 4, 0),
113 [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK3568_GRF_VI_CON0, 4, 4),
[all …]
A Dphy-rockchip-inno-dsidphy.c37 #define PHY_REG(first, second) (FIRST_ADDRESS(first) | \ macro
287 u32 reg = PHY_REG(first, second) << 2; in phy_update_bits()
/drivers/net/dsa/
A Dlan9303_mdio.c18 #define PHY_REG(x) (((x) >> 1) & 0x1f) macro
27 mdio->bus->write(mdio->bus, PHY_ADDR(reg), PHY_REG(reg), val); in lan9303_mdio_real_write()
45 return mdio->bus->read(mdio->bus, PHY_ADDR(reg), PHY_REG(reg)); in lan9303_mdio_real_read()
/drivers/net/ethernet/intel/e1000/
A De1000_hw.h2912 #define PHY_REG(page, reg) \ macro
2916 PHY_REG(769, 17) /* Port General Configuration */
2918 PHY_REG(769, 25) /* Rate Adapter Control Register */
2921 PHY_REG(770, 16) /* KMRN FIFO's control/status register */
2923 PHY_REG(770, 17) /* KMRN Power Management Control Register */
2925 PHY_REG(770, 18) /* KMRN Inband Control Register */
2927 PHY_REG(770, 19) /* KMRN Diagnostic register */
2930 PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */
2933 PHY_REG(776, 18) /* Voltage regulator control register */
2938 PHY_REG(776, 19) /* IGP3 Capability Register */
[all …]
/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
A Dreg.h230 #define PHY_REG 0x02F3 macro

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