| /drivers/gpu/drm/amd/display/dc/dccg/dcn401/ |
| A D | dcn401_dccg.h | 77 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
78 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
79 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
80 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\
112 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
113 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
114 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
115 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\
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| /drivers/gpu/drm/amd/display/dc/dccg/dcn32/ |
| A D | dcn32_dccg.h | 88 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
89 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
90 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
91 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\
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| /drivers/gpu/drm/amd/display/dc/dccg/dcn31/ |
| A D | dcn31_dccg.h | 121 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
122 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
123 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
124 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\
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| /drivers/gpu/drm/amd/display/dc/dccg/dcn314/ |
| A D | dcn314_dccg.h | 119 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
120 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
121 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
122 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\
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| /drivers/gpu/drm/amd/display/dc/dccg/dcn35/ |
| A D | dcn35_dccg.h | 110 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
111 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
112 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
113 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\
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| /drivers/phy/tegra/ |
| A D | Kconfig | 19 Enable this to support the P2U (PIPE to UPHY) that is part of Tegra 19x
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| /drivers/media/platform/qcom/iris/ |
| A D | iris_vpu3x.c | 246 vpp_cycles = mult_frac(mbs_per_second, caps->mb_cycles_vpp, (u32)inst->fw_caps[PIPE].value); in iris_vpu3x_calculate_frequency()
251 if (inst->fw_caps[PIPE].value > 1) in iris_vpu3x_calculate_frequency()
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| A D | iris_platform_sm8250.c | 16 .cap_id = PIPE,
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| A D | iris_platform_common.h | 92 PIPE, enumerator
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| A D | iris_platform_qcs8300.h | 146 .cap_id = PIPE,
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| A D | iris_ctrls.c | 243 u32 work_route = inst->fw_caps[PIPE].value; in iris_set_pipe()
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| A D | iris_platform_gen2.c | 158 .cap_id = PIPE,
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| A D | iris_vdec.c | 479 ret = iris_set_pipe(inst, PIPE); in iris_vdec_process_streamon_output()
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| /drivers/gpu/drm/msm/ |
| A D | NOTES | 38 plane -> PIPE{RGBn,VGn} \
51 plane -> PIPE{RGBn,VIGn} \
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| /drivers/usb/renesas_usbhs/ |
| A D | pipe.c | 127 reg = PIPE ## a ## TRN; \ in usbhsp_pipe_trn_set()
163 reg = PIPE ## a ## TRE; \ in usbhsp_pipe_tre_set()
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_mem_input.h | 55 SRI(DMIF_BUFFER_CONTROL, PIPE, id)
83 SRI(DMIF_BUFFER_CONTROL, PIPE, id)
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| A D | amdgpu_dm_plane.c | 505 AMD_FMT_MOD_SET(PIPE, pipes)); in amdgpu_dm_plane_add_gfx9_modifiers()
519 AMD_FMT_MOD_SET(PIPE, pipes)); in amdgpu_dm_plane_add_gfx9_modifiers()
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| /drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_display.c | 923 AMD_FMT_MOD_SET(PIPE, pipes); in convert_tiling_flags_to_modifier()
|