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Searched refs:PIPE_A (Results 1 – 25 of 46) sorted by relevance

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/drivers/gpu/drm/i915/
A Dintel_gvt_mmio_table.c202 MMIO_D(SPRCTL(PIPE_A)); in iterate_generic_mmio()
203 MMIO_D(SPRLINOFF(PIPE_A)); in iterate_generic_mmio()
204 MMIO_D(SPRSTRIDE(PIPE_A)); in iterate_generic_mmio()
205 MMIO_D(SPRPOS(PIPE_A)); in iterate_generic_mmio()
206 MMIO_D(SPRSIZE(PIPE_A)); in iterate_generic_mmio()
207 MMIO_D(SPRKEYVAL(PIPE_A)); in iterate_generic_mmio()
208 MMIO_D(SPRKEYMSK(PIPE_A)); in iterate_generic_mmio()
209 MMIO_D(SPRSURF(PIPE_A)); in iterate_generic_mmio()
210 MMIO_D(SPRKEYMAX(PIPE_A)); in iterate_generic_mmio()
212 MMIO_D(SPRSCALE(PIPE_A)); in iterate_generic_mmio()
[all …]
A Dintel_clock_gating.c319 intel_uncore_rmw(&i915->uncore, TRANS_CHICKEN1(PIPE_A), in lpt_init_clock_gating()
427 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); in bdw_init_clock_gating()
474 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); in hsw_init_clock_gating()
/drivers/gpu/drm/i915/display/
A Dintel_pch_display.c29 (HAS_PCH_LPT_H(display) && pch_transcoder == PIPE_A); in intel_has_pch_trancoder()
37 return PIPE_A; in intel_crtc_pch_transcoder()
124 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A)) in ibx_sanitize_pch_hdmi_port()
132 val |= SDVO_PIPE_SEL(PIPE_A); in ibx_sanitize_pch_hdmi_port()
143 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A)) in ibx_sanitize_pch_dp_port()
151 val |= DP_PIPE_SEL(PIPE_A); in ibx_sanitize_pch_dp_port()
555 assert_fdi_rx_enabled(display, PIPE_A); in lpt_enable_pch_transcoder()
557 val = intel_de_read(display, TRANS_CHICKEN2(PIPE_A)); in lpt_enable_pch_transcoder()
599 assert_pch_transcoder_disabled(display, PIPE_A); in lpt_pch_enable()
604 ilk_pch_transcoder_set_timings(crtc_state, PIPE_A); in lpt_pch_enable()
[all …]
A Dintel_fdi.c221 case PIPE_A: in ilk_check_fdi_lanes()
448 case PIPE_A: in ivb_update_fdi_bc_bifurcation()
895 intel_de_write(display, FDI_RX_MISC(PIPE_A), in hsw_fdi_link_train()
906 intel_de_posting_read(display, FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
945 intel_de_posting_read(display, FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
951 intel_de_rmw(display, FDI_RX_MISC(PIPE_A), in hsw_fdi_link_train()
953 intel_de_posting_read(display, FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
976 intel_de_posting_read(display, FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
988 intel_de_rmw(display, FDI_RX_MISC(PIPE_A), in hsw_fdi_link_train()
991 intel_de_posting_read(display, FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
[all …]
A Dintel_display_device.c170 [PIPE_A] = CURSOR_A_OFFSET, \
175 [PIPE_A] = CURSOR_A_OFFSET, \
181 [PIPE_A] = CURSOR_A_OFFSET, \
188 [PIPE_A] = CURSOR_A_OFFSET, \
195 [PIPE_A] = CURSOR_A_OFFSET, \
254 .__runtime_defaults.pipe_mask = BIT(PIPE_A), \
479 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
1162 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
1748 display_runtime->num_scalers[PIPE_A] = 2; in __intel_display_device_info_runtime_init()
1772 display_runtime->num_sprites[PIPE_A] = 2; in __intel_display_device_info_runtime_init()
[all …]
A Dskl_watermark.c753 [PIPE_A] = BIT(DBUF_S1),
765 [PIPE_A] = BIT(DBUF_S1),
778 [PIPE_A] = BIT(DBUF_S1),
792 [PIPE_A] = BIT(DBUF_S1),
828 [PIPE_A] = BIT(DBUF_S2),
841 [PIPE_A] = BIT(DBUF_S1),
855 [PIPE_A] = BIT(DBUF_S1),
869 [PIPE_A] = BIT(DBUF_S1),
883 [PIPE_A] = BIT(DBUF_S1),
898 [PIPE_A] = BIT(DBUF_S1),
[all …]
A Dintel_display_limits.h17 PIPE_A = 0, enumerator
34 TRANSCODER_A = PIPE_A,
A Dg4x_hdmi.c406 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false); in intel_disable_hdmi()
407 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); in intel_disable_hdmi()
410 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); in intel_disable_hdmi()
424 intel_wait_for_vblank_if_active(display, PIPE_A); in intel_disable_hdmi()
425 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true); in intel_disable_hdmi()
426 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); in intel_disable_hdmi()
755 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_hdmi_init()
A Dintel_cursor.c310 intel_de_write_fw(display, CURCNTR(display, PIPE_A), 0); in i845_cursor_update_arm()
311 intel_de_write_fw(display, CURBASE(display, PIPE_A), base); in i845_cursor_update_arm()
312 intel_de_write_fw(display, CURSIZE(display, PIPE_A), size); in i845_cursor_update_arm()
313 intel_de_write_fw(display, CURPOS(display, PIPE_A), pos); in i845_cursor_update_arm()
314 intel_de_write_fw(display, CURCNTR(display, PIPE_A), cntl); in i845_cursor_update_arm()
320 intel_de_write_fw(display, CURPOS(display, PIPE_A), pos); in i845_cursor_update_arm()
339 power_domain = POWER_DOMAIN_PIPE(PIPE_A); in i845_cursor_get_hw_state()
344 ret = intel_de_read(display, CURCNTR(display, PIPE_A)) & CURSOR_ENABLE; in i845_cursor_get_hw_state()
346 *pipe = PIPE_A; in i845_cursor_get_hw_state()
A Dintel_display_reg_defs.h40 DISPLAY_INFO(display)->pipe_offsets[PIPE_A] + \
46 DISPLAY_INFO(display)->cursor_offsets[PIPE_A] + \
A Di9xx_wm.c284 case PIPE_A: in vlv_get_fifo_size()
808 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); in g4x_write_wm_values()
814 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | in g4x_write_wm_values()
815 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); in g4x_write_wm_values()
861 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | in vlv_write_wm_values()
1889 case PIPE_A: in vlv_atomic_update_fifo()
3360 if (dirty & WM_DIRTY_PIPE(PIPE_A)) in ilk_write_wm_values()
3665 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA); in g4x_read_wm_values()
3672 wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA); in g4x_read_wm_values()
3673 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA); in g4x_read_wm_values()
[all …]
A Dg4x_dp.c271 *pipe = PIPE_A; in cpt_dp_port_selected()
452 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false); in intel_dp_link_down()
453 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); in intel_dp_link_down()
457 intel_dp->DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) | in intel_dp_link_down()
466 intel_wait_for_vblank_if_active(display, PIPE_A); in intel_dp_link_down()
467 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true); in intel_dp_link_down()
468 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); in intel_dp_link_down()
1379 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_dp_init()
A Dintel_crt.c254 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); in hsw_disable_crt()
283 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); in hsw_post_disable_crt()
295 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); in hsw_pre_pll_enable_crt()
340 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); in hsw_enable_crt()
1064 crt->base.pipe_mask = BIT(PIPE_A); in intel_crt_init()
1130 FDI_RX_CTL(PIPE_A)) & fdi_config; in intel_crt_init()
A Dintel_display_power.h121 ((enum intel_display_power_domain)((pipe) - PIPE_A + POWER_DOMAIN_PIPE_A))
123 ((enum intel_display_power_domain)((pipe) - PIPE_A + POWER_DOMAIN_PIPE_PANEL_FITTER_A))
A Dintel_pipe_crc.c177 case PIPE_A: in vlv_pipe_crc_ctl_reg()
238 case PIPE_A: in vlv_undo_pipe_scramble_reset()
315 pipe_config->hw.active && crtc->pipe == PIPE_A && in intel_crtc_crc_setup_workarounds()
A Dintel_display_irq.c394 i915_enable_pipestat(display, PIPE_A, in i915_enable_asle_pipestat()
543 case PIPE_A: in i9xx_pipestat_irq_ack()
698 intel_pch_fifo_underrun_irq_handler(display, PIPE_A); in ibx_irq_handler()
707 case PIPE_A: in ivb_err_int_pipe_fault_mask()
828 case PIPE_A: in ilk_gtt_fault_pipe_fault_mask()
1285 pipe = PIPE_A; in gen11_dsi_te_interrupt_handler()
1757 case PIPE_A: in vlv_dpinvgtt_pipe_fault_mask()
1908 i915_enable_pipestat(display, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_display_irq_postinstall()
1922 i915_enable_pipestat(display, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in i965_display_irq_postinstall()
1923 i915_enable_pipestat(display, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_display_irq_postinstall()
[all …]
A Dintel_display_power_well.c1089 if ((intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1090 i830_enable_pipe(display, PIPE_A); in i830_pipes_power_well_enable()
1099 i830_disable_pipe(display, PIPE_A); in i830_pipes_power_well_disable()
1105 return intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE && in i830_pipes_power_well_enabled()
1244 if (pipe != PIPE_A) in vlv_display_power_well_init()
1525 assert_pll_disabled(display, PIPE_A); in chv_dpio_cmn_power_well_disable()
1680 enum pipe pipe = PIPE_A; in chv_pipe_power_well_enabled()
1711 enum pipe pipe = PIPE_A; in chv_set_pipe_power_well()
A Dintel_fifo_underrun.c137 u32 bit = (pipe == PIPE_A) ? in ilk_set_fifo_underrun_reporting()
201 u32 bit = (pch_transcoder == PIPE_A) ? in ibx_set_fifo_underrun_reporting()
A Dintel_pps.c45 case PIPE_A: in pps_name()
173 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); in vlv_find_free_pps()
230 pipe = PIPE_A; in vlv_power_sequencer_pipe()
301 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { in vlv_initial_pps_pipe()
1170 if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B)) in vlv_detach_power_sequencer()
1262 if (pipe != PIPE_A && pipe != PIPE_B) in vlv_pps_backlight_initial_pipe()
1265 if (pipe != PIPE_A && pipe != PIPE_B) in vlv_pps_backlight_initial_pipe()
1266 pipe = PIPE_A; in vlv_pps_backlight_initial_pipe()
A Dintel_vga.c62 pipe = PIPE_A; in intel_vga_disable()
A Dintel_dpll.c400 if (display->platform.cherryview && crtc->pipe != PIPE_A) in i9xx_dpll_get_hw_state()
1429 if (crtc->pipe != PIPE_A) in vlv_dpll()
1455 if (crtc->pipe != PIPE_A) in chv_dpll()
1959 if (pipe == PIPE_A) in vlv_prepare_pll()
1965 if (pipe == PIPE_A) in vlv_prepare_pll()
2164 if (pipe != PIPE_A) { in chv_enable_pll()
2238 if (pipe != PIPE_A) in vlv_disable_pll()
2256 if (pipe != PIPE_A) in chv_disable_pll()
A Dintel_dmc.c249 #define PIPE_TO_DMC_ID(pipe) (DMC_FW_PIPEA + ((pipe) - PIPE_A))
471 for (pipe = PIPE_A; pipe <= PIPE_D; pipe++) in adlp_pipedmc_clock_gating_wa()
488 MTL_PIPEDMC_GATING_DIS(PIPE_A) | in mtl_pipedmc_clock_gating_wa()
871 PIPE_A_DMC_W2_PTS_CONFIG_SELECT(PIPE_A)); in intel_dmc_load_program()
/drivers/gpu/drm/i915/gvt/
A Dhandlers.c708 vgpu->id, pipe_name(PIPE_A), new_rate); in vgpu_update_refresh_rate()
2303 MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL, in init_generic_mmio_info()
2312 MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL, in init_generic_mmio_info()
2490 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
2492 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
2494 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
2655 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2656 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2657 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2670 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
[all …]
A Dreg.h68 (((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \
78 (((reg) == 0x50080 || (reg) == 0x50090) ? (PIPE_A) : \
A Ddisplay.c59 pipe = PIPE_A; in get_edp_pipe()
90 pipe < PIPE_A || pipe >= I915_MAX_PIPES)) in pipe_is_enabled()
642 [PIPE_A] = PIPE_A_VBLANK, in emulate_vblank_on_pipe()
648 if (pipe < PIPE_A || pipe > PIPE_C) in emulate_vblank_on_pipe()

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