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Searched refs:PIXEL_RATE_DIV_NA (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dccg/dcn32/
A Ddcn32_dccg.c65 uint32_t val_k1 = PIXEL_RATE_DIV_NA, val_k2 = PIXEL_RATE_DIV_NA; in dccg32_get_pixel_rate_div()
67 *k1 = PIXEL_RATE_DIV_NA; in dccg32_get_pixel_rate_div()
68 *k2 = PIXEL_RATE_DIV_NA; in dccg32_get_pixel_rate_div()
107 uint32_t cur_k1 = PIXEL_RATE_DIV_NA; in dccg32_set_pixel_rate_div()
108 uint32_t cur_k2 = PIXEL_RATE_DIV_NA; in dccg32_set_pixel_rate_div()
112 if (k1 == PIXEL_RATE_DIV_NA || k2 == PIXEL_RATE_DIV_NA) { in dccg32_set_pixel_rate_div()
/drivers/gpu/drm/amd/display/dc/dccg/dcn314/
A Ddcn314_dccg.c65 uint32_t val_k1 = PIXEL_RATE_DIV_NA, val_k2 = PIXEL_RATE_DIV_NA; in dccg314_get_pixel_rate_div()
67 *k1 = PIXEL_RATE_DIV_NA; in dccg314_get_pixel_rate_div()
68 *k2 = PIXEL_RATE_DIV_NA; in dccg314_get_pixel_rate_div()
107 uint32_t cur_k1 = PIXEL_RATE_DIV_NA; in dccg314_set_pixel_rate_div()
108 uint32_t cur_k2 = PIXEL_RATE_DIV_NA; in dccg314_set_pixel_rate_div()
112 if (k1 == PIXEL_RATE_DIV_NA || k2 == PIXEL_RATE_DIV_NA) { in dccg314_set_pixel_rate_div()
/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
A Ddcn314_hwseq.c357 if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA)) in dcn314_calculate_dccg_k1_k2_values()
370 unsigned int k1_div = PIXEL_RATE_DIV_NA; in dcn314_calculate_pix_rate_divider()
371 unsigned int k2_div = PIXEL_RATE_DIV_NA; in dcn314_calculate_pix_rate_divider()
/drivers/gpu/drm/amd/display/dc/dccg/dcn35/
A Ddcn35_dccg.c1215 uint32_t val_k1 = PIXEL_RATE_DIV_NA, val_k2 = PIXEL_RATE_DIV_NA; in dccg35_get_pixel_rate_div()
1217 *k1 = PIXEL_RATE_DIV_NA; in dccg35_get_pixel_rate_div()
1218 *k2 = PIXEL_RATE_DIV_NA; in dccg35_get_pixel_rate_div()
1257 uint32_t cur_k1 = PIXEL_RATE_DIV_NA; in dccg35_set_pixel_rate_div()
1258 uint32_t cur_k2 = PIXEL_RATE_DIV_NA; in dccg35_set_pixel_rate_div()
1263 if (k1 == PIXEL_RATE_DIV_NA || k2 == PIXEL_RATE_DIV_NA) { in dccg35_set_pixel_rate_div()
/drivers/gpu/drm/amd/display/dc/inc/hw/
A Ddccg.h71 PIXEL_RATE_DIV_NA = 0xF enumerator
/drivers/gpu/drm/amd/display/dc/dccg/dcn401/
A Ddcn401_dccg.c126 uint32_t val_tmds_div = PIXEL_RATE_DIV_NA; in dccg401_get_pixel_rate_div()
164 uint32_t cur_tmds_div = PIXEL_RATE_DIV_NA; in dccg401_set_pixel_rate_div()
/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
A Ddcn32_hwseq.c1213 if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA)) in dcn32_calculate_dccg_k1_k2_values()
1226 unsigned int k1_div = PIXEL_RATE_DIV_NA; in dcn32_calculate_pix_rate_divider()
1227 unsigned int k2_div = PIXEL_RATE_DIV_NA; in dcn32_calculate_pix_rate_divider()
/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
A Ddcn401_hwseq.c701 if (*tmds_div == PIXEL_RATE_DIV_NA) in dcn401_calculate_dccg_tmds_div_value()
760 unsigned int tmds_div = PIXEL_RATE_DIV_NA; in dcn401_enable_stream_timing()
761 unsigned int unused_div = PIXEL_RATE_DIV_NA; in dcn401_enable_stream_timing()
943 unsigned int tmds_div = PIXEL_RATE_DIV_NA; in dcn401_enable_stream()
944 unsigned int unused_div = PIXEL_RATE_DIV_NA; in dcn401_enable_stream()

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