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Searched refs:PLANE_CTL (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/i915/display/
A Dskl_universal_plane.c882 intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), 0); in skl_plane_disable_arm()
914 intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), 0); in icl_plane_disable_arm()
933 ret = intel_de_read(display, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE; in skl_plane_get_hw_state()
1476 intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), in skl_plane_update_arm()
1658 intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), in icl_plane_update_arm()
1670 error->ctl = intel_de_read(display, PLANE_CTL(crtc->pipe, plane->id)); in skl_plane_capture_error()
1697 intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), in skl_plane_async_flip()
2801 plane_ctl = intel_de_read(display, PLANE_CTL(plane->pipe, plane->id)); in skl_disable_tiling()
2814 intel_de_write_fw(display, PLANE_CTL(plane->pipe, plane->id), plane_ctl); in skl_disable_tiling()
3049 val = intel_de_read(display, PLANE_CTL(pipe, plane_id)); in skl_get_initial_plane_config()
A Dskl_universal_plane_regs.h35 #define PLANE_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ macro
/drivers/gpu/drm/i915/
A Dintel_gvt_mmio_table.c1041 MMIO_D(PLANE_CTL(PIPE_A, 2)); in iterate_skl_plus_mmio()
1042 MMIO_D(PLANE_CTL(PIPE_B, 2)); in iterate_skl_plus_mmio()
1043 MMIO_D(PLANE_CTL(PIPE_C, 2)); in iterate_skl_plus_mmio()

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