Searched refs:PLL_ENABLE (Results 1 – 7 of 7) sorted by relevance
| /drivers/phy/ti/ |
| A D | phy-am654-serdes.c | 188 PLL_ENABLE, enumerator
229 [PLL_ENABLE] = REG_FIELD(WIZ_PLL_CTRL, 29, 31),
251 ret = regmap_field_write(phy->fields[PLL_ENABLE], PLL_ENABLE_STATE); in serdes_am654_enable_pll()
264 ret = regmap_field_write(phy->fields[PLL_ENABLE], PLL_DISABLE_STATE); in serdes_am654_disable_pll()
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| /drivers/clk/spear/ |
| A D | clk-vco-pll.c | 47 #define PLL_ENABLE 2 macro
312 parent_name, 0, mode_reg, PLL_ENABLE, 0, lock); in clk_register_vco_pll()
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| /drivers/clk/tegra/ |
| A D | clk-tegra210.c | 322 #define PLL_ENABLE (1 << 30) macro
838 if (val & PLL_ENABLE) { in tegra210_plla_set_defaults()
891 PLL_ENABLE) { in tegra210_plld_set_defaults()
944 if (val & PLL_ENABLE) { in plldss_defaults()
1063 if (val & PLL_ENABLE) { in tegra210_pllre_set_defaults()
1188 if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) { in tegra210_pllx_set_defaults()
1241 if (val & PLL_ENABLE) { in tegra210_pllmb_set_defaults()
1302 if (val & PLL_ENABLE) { in tegra210_pllp_set_defaults()
1365 if (val & PLL_ENABLE) { in tegra210_pllu_set_defaults()
2923 reg |= PLL_ENABLE; in tegra210_enable_pllu()
[all …]
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| /drivers/clk/imx/ |
| A D | clk-imx6q.c | 389 #define PLL_ENABLE BIT(13) macro
417 reg &= ~PLL_ENABLE; in disable_anatop_clocks()
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| /drivers/gpu/drm/i915/display/ |
| A D | intel_dpll_mgr.c | 3559 if (!(val & PLL_ENABLE)) in mg_pll_get_hw_state()
3624 if (!(val & PLL_ENABLE)) in dkl_pll_get_hw_state()
3696 if (!(val & PLL_ENABLE)) in icl_pll_get_hw_state()
3925 intel_de_rmw(display, enable_reg, 0, PLL_ENABLE); in icl_pll_enable()
4038 intel_de_rmw(display, enable_reg, PLL_ENABLE, 0); in icl_pll_disable()
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| A D | intel_snps_phy.c | 1849 intel_de_rmw(display, enable_reg, 0, PLL_ENABLE); in intel_mpllb_enable()
1894 intel_de_rmw(display, enable_reg, PLL_ENABLE, 0); in intel_mpllb_disable()
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| A D | intel_display_regs.h | 2653 #define PLL_ENABLE REG_BIT(31) macro
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