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Searched refs:PMC (Results 1 – 24 of 24) sorted by relevance

/drivers/video/fbdev/riva/
A Dnvreg.h126 #define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
127 #define PMC_Read(reg) DEVICE_READ(PMC,reg)
128 #define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
129 #define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)
130 #define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value)
131 #define PMC_Mask(mask) DEVICE_MASK(PMC,mask)
133 #define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
134 #define PMC_Read(reg) DEVICE_READ(PMC,reg)
135 #define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
136 #define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)
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A Dnv_driver.c167 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) in riva_get_memlen()
168 && ((NV_RD32(chip->PMC, 0x00000000)&0x0F)>=0x02)) { in riva_get_memlen()
281 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) in riva_get_maxdclk()
282 && ((NV_RD32(chip->PMC,0x00000000)&0x0F) >= 0x02)) { in riva_get_maxdclk()
330 par->riva.PMC = in riva_common_setup()
A Driva_hw.c1379 LOAD_FIXED_STATE(Riva,PMC); in LoadStateExt()
1533 NV_WR32(chip->PMC, 0x00008704, 1); in LoadStateExt()
1534 NV_WR32(chip->PMC, 0x00008140, 0); in LoadStateExt()
1535 NV_WR32(chip->PMC, 0x00008920, 0); in LoadStateExt()
1536 NV_WR32(chip->PMC, 0x00008924, 0); in LoadStateExt()
1537 NV_WR32(chip->PMC, 0x00008908, 0x01ffffff); in LoadStateExt()
1538 NV_WR32(chip->PMC, 0x0000890C, 0x01ffffff); in LoadStateExt()
1539 NV_WR32(chip->PMC, 0x00001588, 0); in LoadStateExt()
1691 NV_WR32(chip->PMC, 0x00000140, chip->EnableIRQ & 0x01); in LoadStateExt()
2079 if(!(NV_RD32(chip->PMC, 0x00000004) & 0x01000001)) in nv10GetConfig()
[all …]
A Driva_hw.h452 volatile U032 __iomem *PMC; member
A Dfbdev.c298 tmp_pmc = NV_RD32(par->riva.PMC, 0x10F0) & 0x0000FFFF; in riva_bl_update_status()
306 NV_WR32(par->riva.PMC, 0x10F0, tmp_pmc); in riva_bl_update_status()
/drivers/platform/x86/intel/pmc/
A DKconfig7 tristate "Intel PMC Core driver"
17 tasks in the PMC in order to enable transition into the SLPS0 state.
27 - PMC quirks as needed to enable SLPS0/S0ix
/drivers/video/fbdev/nvidia/
A Dnv_hw.c147 pll = NV_RD32(par->PMC, 0x4020); in nvGetClocks()
149 pll = NV_RD32(par->PMC, 0x4024); in nvGetClocks()
162 pll = NV_RD32(par->PMC, 0x4000); in nvGetClocks()
164 pll = NV_RD32(par->PMC, 0x4004); in nvGetClocks()
1266 NV_WR32(par->PMC, 0x1700, in NVLoadStateExt()
1270 NV_WR32(par->PMC, 0x170C, in NVLoadStateExt()
1525 NV_WR32(par->PMC, 0x8704, 1); in NVLoadStateExt()
1526 NV_WR32(par->PMC, 0x8140, 0); in NVLoadStateExt()
1527 NV_WR32(par->PMC, 0x8920, 0); in NVLoadStateExt()
1528 NV_WR32(par->PMC, 0x8924, 0); in NVLoadStateExt()
[all …]
A Dnv_backlight.c57 tmp_pmc = NV_RD32(par->PMC, 0x10F0) & 0x0000FFFF; in nvidia_bl_update_status()
70 NV_WR32(par->PMC, 0x10F0, tmp_pmc); in nvidia_bl_update_status()
A Dnv_setup.c234 if (!(NV_RD32(par->PMC, 0x0004) & 0x01000001)) { in nv10GetConfig()
235 NV_WR32(par->PMC, 0x0004, 0x01000001); in nv10GetConfig()
303 par->PMC = par->REGS + (0x00000000 / 4); in NVCommonSetup()
A Dnv_type.h164 volatile u32 __iomem *PMC; member
/drivers/perf/
A Dfsl_imx9_ddr_perf.c46 #define PMC(n) (0x40 + 0x18 + (0x10 * n)) macro
368 writel(0, pmu->base + PMC(counter) + 0x4); in ddr_perf_clear_counter()
369 writel(0, pmu->base + PMC(counter)); in ddr_perf_clear_counter()
371 writel(0, pmu->base + PMC(counter)); in ddr_perf_clear_counter()
381 val = readl_relaxed(pmu->base + PMC(counter)); in ddr_perf_read_counter()
387 val_upper = readl_relaxed(pmu->base + PMC(counter) + 0x4); in ddr_perf_read_counter()
388 val_lower = readl_relaxed(pmu->base + PMC(counter)); in ddr_perf_read_counter()
389 } while (val_upper != readl_relaxed(pmu->base + PMC(counter) + 0x4)); in ddr_perf_read_counter()
/drivers/platform/x86/amd/pmc/
A DKconfig3 # AMD PMC Driver
7 tristate "AMD SoC PMC driver"
/drivers/usb/typec/mux/
A DKconfig29 tristate "Intel PMC mux control"
35 Driver for USB muxes controlled by Intel PMC FW. Intel PMC FW can
/drivers/net/can/esd/
A DKconfig9 M.2 PCIe, CPCIserial, PMC, XMC (see https://esd.eu/en)
/drivers/platform/mellanox/
A DKconfig104 Say y here to enable PMC support. The PMC driver provides access
/drivers/pinctrl/renesas/
A Dpinctrl-rzg2l.c136 #define PMC(off) (0x0200 + (off)) macro
529 reg = readb(pctrl->base + PMC(off)); in rzg2l_pinctrl_set_pfc_mode()
530 writeb(reg & ~BIT(pin), pctrl->base + PMC(off)); in rzg2l_pinctrl_set_pfc_mode()
538 reg = readb(pctrl->base + PMC(off)); in rzg2l_pinctrl_set_pfc_mode()
539 writeb(reg | BIT(pin), pctrl->base + PMC(off)); in rzg2l_pinctrl_set_pfc_mode()
1706 reg8 = readb(pctrl->base + PMC(off)); in rzg2l_gpio_request()
1708 pctrl->data->pmc_writeb(pctrl, reg8, PMC(off)); in rzg2l_gpio_request()
1744 if (!(readb(pctrl->base + PMC(off)) & BIT(bit))) { in rzg2l_gpio_get_direction()
2551 reg8 = readb(pctrl->base + PMC(off)); in rzg2l_gpio_interrupt_input_mode()
3132 writeb(pmc, pctrl->base + PMC(off)); in rzg2l_pinctrl_pm_setup_pfc()
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/drivers/scsi/smartpqi/
A DKconfig7 # Copyright (c) 2016 PMC-Sierra, Inc.
/drivers/net/can/sja1000/
A DKconfig80 - esd CAN-PCI/PMC/266
/drivers/platform/x86/intel/
A DKconfig50 Power Management Event (PME) to the Power Management Controller (PMC)
/drivers/scsi/
A DKconfig1488 tristate "PMC SIERRA Linux MaxRAID adapter support"
1492 This driver supports the PMC SIERRA MaxRAID adapters.
1495 tristate "PMC-Sierra SPC 8001 SAS/SATA Based Host Adapter driver"
1499 This driver supports PMC-Sierra PCIE SAS/SATA 8x6G SPC 8001 chip
/drivers/mfd/
A DKconfig774 tristate "Intel PMC Driver for Broxton"
781 This driver provides support for the PMC (Power Management
782 Controller) on Intel Broxton and Apollo Lake. The PMC is a
785 for iTCO watchdog and telemetry that are part of the PMC.
/drivers/comedi/
A DKconfig905 tristate "General Standards PCI-HPDI32 / PMC-HPDI32 support"
908 digital interface rs485 boards PCI-HPDI32 and PMC-HPDI32.
/drivers/iio/adc/
A DKconfig708 tristate "GE HealthCare PMC ADC driver"
711 Say yes here to build support for the GE HealthCare PMC 16-bit
/drivers/platform/x86/
A DKconfig953 and SCU (sometimes called PMC as well). The driver currently

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