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Searched refs:PORT_A (Results 1 – 25 of 38) sorted by relevance

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/drivers/gpu/drm/i915/display/
A Dg4x_dp.c133 if (display->platform.ivybridge && port == PORT_A) { in intel_dp_prepare()
288 if (display->platform.ivybridge && port == PORT_A) in g4x_dp_port_enabled()
290 else if (HAS_PCH_CPT(display) && port != PORT_A) in g4x_dp_port_enabled()
354 if (HAS_PCH_CPT(display) && port != PORT_A) { in intel_dp_get_config()
394 if (port == PORT_A) { in intel_dp_get_config()
428 (HAS_PCH_CPT(display) && port != PORT_A)) { in intel_dp_link_down()
563 if (port == PORT_A) in g4x_post_disable_dp()
733 if (port == PORT_A) in g4x_pre_enable_dp()
1345 (HAS_PCH_CPT(display) && port != PORT_A)) in g4x_dp_init()
1392 if (port == PORT_A) in g4x_dp_init()
[all …]
A Dintel_display_device.c263 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C), /* DVO A/B/C */
833 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C)
939 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D),
1036 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
1053 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
1076 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
1115 .__runtime_defaults.port_mask = BIT(PORT_A) |
1173 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
1238 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D_XELPD) |
1341 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | \
[all …]
A Dvlv_dsi.c343 intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); in glk_dsi_enable_io()
484 intel_de_rmw(display, VLV_MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD); in vlv_dsi_device_ready()
579 BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(PORT_A); in vlv_dsi_clear_device_ready()
597 if ((display->platform.broxton || port == PORT_A) && in vlv_dsi_clear_device_ready()
643 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { in intel_dsi_port_enable()
997 *pipe = port == PORT_A ? PIPE_A : PIPE_B; in intel_dsi_get_hw_state()
1331 tmp = intel_de_read(display, MIPI_CTRL(display, PORT_A)); in intel_dsi_prepare()
1333 intel_de_write(display, MIPI_CTRL(display, PORT_A), in intel_dsi_prepare()
1432 MIPI_INIT_COUNT(display, port == PORT_A ? PORT_C : PORT_A), in intel_dsi_prepare()
1962 else if (port == PORT_A) in vlv_dsi_init()
[all …]
A Dintel_ddi.c1925 case PORT_A: in bxt_ddi_get_pll()
3387 [PORT_A] = TRANSCODER_EDP, in gen9_chicken_trans_reg_by_port()
3397 port = PORT_A; in gen9_chicken_trans_reg_by_port()
4862 if (dig_port->base.port != PORT_A) in intel_ddi_a_force_4_lanes()
4917 return HPD_PORT_A + port - PORT_A; in xelpd_hpd_pin()
4925 return HPD_PORT_A + port - PORT_A; in dg1_hpd_pin()
4963 return HPD_PORT_A + port - PORT_A; in ehl_hpd_pin()
4971 return HPD_PORT_A + port - PORT_A; in skl_hpd_pin()
5028 case PORT_A: in port_strap_detected()
5381 if (port == PORT_A) in intel_ddi_init()
[all …]
A Dintel_display_limits.h95 PORT_A = 0, enumerator
A Dintel_bios.c1666 panel->vbt.dsi.bl_ports = BIT(PORT_A); in parse_dsi_backlight_ports()
1682 panel->vbt.dsi.cabc_ports = BIT(PORT_A); in parse_dsi_backlight_ports()
1690 BIT(PORT_A) | BIT(port_bc); in parse_dsi_backlight_ports()
2327 for (port = PORT_A; port < n_ports; port++) { in __dvo_port_to_port()
2348 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, in dvo_port_to_port()
2363 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, in dvo_port_to_port()
2374 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, in dvo_port_to_port()
2383 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, in dvo_port_to_port()
2421 return PORT_A; in dsi_dvo_port_to_port()
2937 if (port != PORT_A && port != PORT_E) in init_vbt_missing_defaults()
[all …]
A Dicl_dsi.c98 if (port == PORT_A) in dsi_port_to_transcoder()
227 port = PORT_A; in icl_dsi_frame_update()
397 port == PORT_A ? in get_dsi_io_power_domains()
1396 port == PORT_A ? in gen11_dsi_disable_io_power()
1534 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) in gen11_dsi_get_cmd_mode_config()
1986 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); in icl_dsi_init()
A Dintel_display.h101 case PORT_A: in port_identifier()
212 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)
A Dintel_combo_phy.c165 bool ddi_a_present = intel_bios_is_port_present(display, PORT_A); in ehl_vbt_ddi_d_present()
A Dintel_display_power.c2366 .port_start = PORT_A,
2382 .port_start = PORT_A,
2409 .port_start = PORT_A,
2436 .port_start = PORT_A,
A Dintel_display_irq.c1269 PORT_A : PORT_B; in gen11_dsi_te_interrupt_handler()
1270 dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1; in gen11_dsi_te_interrupt_handler()
1301 port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A; in gen11_dsi_te_interrupt_handler()
1692 port = PORT_A; in gen11_dsi_configure_te()
A Dintel_cx0_phy_regs.h33 (port >= PORT_TC1 ? port : PORT_TC4 + 1 + port - PORT_A)
A Dintel_dvo.c85 .port = PORT_A,
A Dvlv_dsi_regs.h16 #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */
A Dintel_dpio_phy.c186 [DPIO_CH0] = { .port = PORT_A },
209 [DPIO_CH0] = { .port = PORT_A },
A Dintel_audio.c635 if (drm_WARN_ON(display->drm, port == PORT_A)) in ibx_audio_codec_disable()
671 if (drm_WARN_ON(display->drm, port == PORT_A)) in ibx_audio_codec_enable()
A Dvlv_dsi_pll.c193 if (intel_dsi->ports & (1 << PORT_A)) in vlv_dsi_pll_compute()
A Dintel_pch_refclk.c517 if (encoder->port == PORT_A) in ilk_init_pch_refclk()
/drivers/gpu/drm/i915/gvt/
A Ddisplay.c219 for (port = PORT_A; port <= PORT_C; port++) { in emulate_monitor_status_change()
279 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { in emulate_monitor_status_change()
285 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |= in emulate_monitor_status_change()
287 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &= in emulate_monitor_status_change()
290 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |= in emulate_monitor_status_change()
294 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= in emulate_monitor_status_change()
296 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &= in emulate_monitor_status_change()
502 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { in emulate_monitor_status_change()
509 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED; in emulate_monitor_status_change()
709 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { in intel_vgpu_emulate_hotplug()
A Dmmio.c275 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &= in intel_vgpu_reset_mmio()
277 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |= in intel_vgpu_reset_mmio()
A Dhandlers.c560 case PORT_A: in bxt_vgpu_get_dp_bitrate()
958 calc_index(offset, DP_TP_CTL(PORT_A), DP_TP_CTL(PORT_B), DP_TP_CTL(PORT_E))
1179 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS))
2370 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
2376 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2382 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); in init_generic_mmio_info()
2785 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT, in init_bxt_mmio_info()
/drivers/staging/media/tegra-video/
A Dcsi.h29 PORT_A = 0, enumerator
A Dtegra210.c1016 val = ((portno & 1) == PORT_A) ? in tegra210_csi_port_start_streaming()
1109 val = ((portno & 1) == PORT_A) ? in tegra210_csi_port_stop_streaming()
/drivers/staging/media/ipu7/
A Dipu7-isys-csi-phy.c26 #define PORT_A 0U macro
574 val = (id == PORT_A) ? 3 : 0; in ipu7_isys_dphy_config()
901 if (aggregation && id != PORT_A) in ipu7_isys_phy_config()
962 if (!is_ipu7(isys->adev->isp->hw_ver) && lanes > 2 && id == PORT_A) { in ipu7_isys_csi_phy_powerup()
1032 csi2->nlanes > 2U && csi2->port == PORT_A) in ipu7_isys_csi_phy_powerdown()
/drivers/gpu/drm/i915/
A Dintel_gvt_mmio_table.c497 MMIO_D(PORT_CLK_SEL(PORT_A)); in iterate_generic_mmio()
528 MMIO_D(DDI_BUF_CTL(PORT_A)); in iterate_generic_mmio()
533 MMIO_D(DP_TP_CTL(PORT_A)); in iterate_generic_mmio()
538 MMIO_D(DP_TP_STATUS(PORT_A)); in iterate_generic_mmio()
1140 MMIO_D(BXT_PHY_CTL(PORT_A)); in iterate_bxt_mmio()
1143 MMIO_D(BXT_PORT_PLL_ENABLE(PORT_A)); in iterate_bxt_mmio()

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