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Searched refs:PORT_B (Results 1 – 25 of 32) sorted by relevance

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/drivers/gpu/drm/i915/gvt/
A Ddisplay.c315 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |= in emulate_monitor_status_change()
317 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &= in emulate_monitor_status_change()
324 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= in emulate_monitor_status_change()
326 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= in emulate_monitor_status_change()
331 (PORT_B << TRANS_DDI_PORT_SHIFT) | in emulate_monitor_status_change()
362 (PORT_B << TRANS_DDI_PORT_SHIFT) | in emulate_monitor_status_change()
418 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_B); in emulate_monitor_status_change()
422 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B); in emulate_monitor_status_change()
429 (PORT_B << TRANS_DDI_PORT_SHIFT) | in emulate_monitor_status_change()
432 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &= in emulate_monitor_status_change()
[all …]
A Dedid.c92 port = PORT_B; in cnp_get_port_from_gmbus0()
108 port = PORT_B; in bxt_get_port_from_gmbus0()
126 port = PORT_B; in get_port_from_gmbus0()
A Dmmio.c280 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &= in intel_vgpu_reset_mmio()
282 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |= in intel_vgpu_reset_mmio()
A Dvgpu.c376 ret = intel_gvt_set_edid(vgpu, PORT_B); in intel_gvt_create_vgpu()
A Dhandlers.c564 case PORT_B: in bxt_vgpu_get_dp_bitrate()
671 if (port != PORT_B && port != PORT_D) { in vgpu_update_refresh_rate()
958 calc_index(offset, DP_TP_CTL(PORT_A), DP_TP_CTL(PORT_B), DP_TP_CTL(PORT_E))
2371 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
2377 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2383 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); in init_generic_mmio_info()
2787 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT, in init_bxt_mmio_info()
/drivers/gpu/drm/i915/display/
A Dintel_display_device.c272 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
282 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
292 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
307 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) /* SDVO B/C */
403 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */
833 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C)
1036 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
1053 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
1076 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
1173 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
[all …]
A Dintel_pch_display.c85 assert_pch_dp_disabled(display, pipe, PORT_B, PCH_DP_B); in assert_pch_ports_disabled()
100 assert_pch_hdmi_disabled(display, pipe, PORT_B, PCH_HDMIB); in assert_pch_ports_disabled()
169 ibx_sanitize_pch_dp_port(display, PORT_B, PCH_DP_B); in ibx_sanitize_pch_ports()
174 ibx_sanitize_pch_hdmi_port(display, PORT_B, PCH_HDMIB); in ibx_sanitize_pch_ports()
438 drm_WARN_ON(display->drm, port < PORT_B || port > PORT_D); in ilk_pch_enable()
A Dintel_lpe_audio.c341 ppdata = &pdata->port[port - PORT_B]; in intel_lpe_audio_notify()
368 pdata->notify_audio_lpe(display->audio.lpe.platdev, port - PORT_B); in intel_lpe_audio_notify()
A Dintel_display_limits.h96 PORT_B, enumerator
A Dintel_dpio_phy.c176 [DPIO_CH0] = { .port = PORT_B },
199 [DPIO_CH0] = { .port = PORT_B },
665 case PORT_B: in vlv_dig_port_to_channel()
679 case PORT_B: in vlv_dig_port_to_phy()
1181 case PORT_B: in vlv_wait_port_ready()
A Dicl_dsi.c229 port = PORT_B; in icl_dsi_frame_update()
1097 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) in gen11_dsi_config_util_pin()
1522 if (intel_dsi->ports == BIT(PORT_B)) in gen11_dsi_is_periodic_cmd_mode()
1534 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) in gen11_dsi_get_cmd_mode_config()
1537 else if (intel_dsi->ports == BIT(PORT_B)) in gen11_dsi_get_cmd_mode_config()
1663 if (intel_dsi->ports == BIT(PORT_B)) in gen11_dsi_compute_config()
1986 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); in icl_dsi_init()
A Dintel_sdvo.c234 if (intel_sdvo->base.port == PORT_B) in intel_sdvo_write_sdvox()
412 #define SDVO_NAME(svdo) ((svdo)->base.port == PORT_B ? "SDVOB" : "SDVOC")
1627 if (intel_sdvo->base.port == PORT_B) in intel_sdvo_pre_enable()
2620 if (sdvo->base.port == PORT_B) in intel_sdvo_select_ddc_bus()
2643 if (sdvo->base.port == PORT_B) in intel_sdvo_select_i2c_bus()
2687 if (sdvo->base.port == PORT_B) { in intel_sdvo_get_target_addr()
2714 if (sdvo->base.port == PORT_B) in intel_sdvo_get_target_addr()
3366 return port == PORT_B; in is_sdvo_port_valid()
3368 return port == PORT_B || port == PORT_C; in is_sdvo_port_valid()
3464 if (intel_sdvo->base.port == PORT_B) in intel_sdvo_init()
A Dintel_audio_regs.h161 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_BASE_PORT3(VLV_DISPLAY_BASE, (port) - PORT_B, \
A Dg4x_hdmi.c661 return port == PORT_B || port == PORT_C; in is_hdmi_port_valid()
663 return port == PORT_B || port == PORT_C || port == PORT_D; in is_hdmi_port_valid()
A Dintel_dsi_vbt.c92 if (intel_dsi->ports & BIT(PORT_B)) in intel_dsi_seq_port_to_port()
93 return PORT_B; in intel_dsi_seq_port_to_port()
A Dintel_bios.c1654 enum port port_bc = DISPLAY_VER(display) >= 11 ? PORT_B : PORT_C; in parse_dsi_backlight_ports()
2349 [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, in dvo_port_to_port()
2364 [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, in dvo_port_to_port()
2375 [PORT_B] = { -1 }, in dvo_port_to_port()
2384 [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, in dvo_port_to_port()
2424 return PORT_B; in dsi_dvo_port_to_port()
A Dintel_hdmi.c2722 case PORT_B: in chv_encoder_to_ddc_pin()
2745 case PORT_B: in bxt_encoder_to_ddc_pin()
2765 case PORT_B: in cnp_encoder_to_ddc_pin()
2869 WARN_ON(encoder->port == PORT_B || encoder->port == PORT_C); in adls_encoder_to_ddc_pin()
2887 case PORT_B: in g4x_encoder_to_ddc_pin()
A Dintel_dvo.c107 .port = PORT_B,
A Dintel_pipe_crc.c106 case PORT_B: in i9xx_pipe_crc_auto_source()
A Dintel_display.c7773 found = intel_sdvo_init(display, PCH_SDVOB, PORT_B); in intel_setup_outputs()
7775 g4x_hdmi_init(display, PCH_HDMIB, PORT_B); in intel_setup_outputs()
7777 g4x_dp_init(display, PCH_DP_B, PORT_B); in intel_setup_outputs()
7812 has_edp = intel_dp_is_port_edp(display, PORT_B); in intel_setup_outputs()
7813 has_port = intel_bios_is_port_present(display, PORT_B); in intel_setup_outputs()
7815 has_edp &= g4x_dp_init(display, VLV_DP_B, PORT_B); in intel_setup_outputs()
7817 g4x_hdmi_init(display, VLV_HDMIB, PORT_B); in intel_setup_outputs()
7852 found = intel_sdvo_init(display, GEN3_SDVOB, PORT_B); in intel_setup_outputs()
7856 g4x_hdmi_init(display, GEN4_HDMIB, PORT_B); in intel_setup_outputs()
7860 g4x_dp_init(display, DP_B, PORT_B); in intel_setup_outputs()
A Dintel_display_debugfs.c859 lpsp_capable = encoder->port <= PORT_B; in i915_lpsp_capability_show()
866 lpsp_capable = encoder->port <= PORT_B; in i915_lpsp_capability_show()
A Dintel_display_irq.c1269 PORT_A : PORT_B; in gen11_dsi_te_interrupt_handler()
1301 port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A; in gen11_dsi_te_interrupt_handler()
1690 port = PORT_B; in gen11_dsi_configure_te()
/drivers/staging/media/ipu7/
A Dipu7-isys-csi-phy.c27 #define PORT_B 1U macro
511 id == PORT_B || id == PORT_C) { in ipu7_isys_dphy_config()
976 ipu7_isys_csi_phy_reset(isys, PORT_B); in ipu7_isys_csi_phy_powerup()
978 gpreg_write(isys, PORT_B, PHY_LANE_CONTROL_EN, 0x3); in ipu7_isys_csi_phy_powerup()
1010 gpreg_write(isys, PORT_B, PHY_RESET, 1); in ipu7_isys_csi_phy_powerup()
1011 gpreg_write(isys, PORT_B, PHY_SHUTDOWN, 1); in ipu7_isys_csi_phy_powerup()
1012 dwc_csi_write(isys, PORT_B, DPHY_RSTZ, 1); in ipu7_isys_csi_phy_powerup()
1013 dwc_csi_write(isys, PORT_B, PHY_SHUTDOWNZ, 1); in ipu7_isys_csi_phy_powerup()
1014 dwc_csi_write(isys, PORT_B, CSI2_RESETN, 1); in ipu7_isys_csi_phy_powerup()
1015 ret = ipu7_isys_phy_ready(isys, PORT_B); in ipu7_isys_csi_phy_powerup()
[all …]
/drivers/staging/media/tegra-video/
A Dcsi.h30 PORT_B, enumerator
/drivers/gpu/drm/i915/
A Dintel_gvt_mmio_table.c498 MMIO_D(PORT_CLK_SEL(PORT_B)); in iterate_generic_mmio()
529 MMIO_D(DDI_BUF_CTL(PORT_B)); in iterate_generic_mmio()
534 MMIO_D(DP_TP_CTL(PORT_B)); in iterate_generic_mmio()
539 MMIO_D(DP_TP_STATUS(PORT_B)); in iterate_generic_mmio()
1141 MMIO_D(BXT_PHY_CTL(PORT_B)); in iterate_bxt_mmio()
1144 MMIO_D(BXT_PORT_PLL_ENABLE(PORT_B)); in iterate_bxt_mmio()

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