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Searched refs:PORT_C (Results 1 – 25 of 26) sorted by relevance

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/drivers/gpu/drm/i915/gvt/
A Ddisplay.c219 for (port = PORT_A; port <= PORT_C; port++) { in emulate_monitor_status_change()
346 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |= in emulate_monitor_status_change()
348 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &= in emulate_monitor_status_change()
351 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |= in emulate_monitor_status_change()
355 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= in emulate_monitor_status_change()
357 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= in emulate_monitor_status_change()
444 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_C); in emulate_monitor_status_change()
448 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C); in emulate_monitor_status_change()
455 (PORT_C << TRANS_DDI_PORT_SHIFT) | in emulate_monitor_status_change()
458 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &= in emulate_monitor_status_change()
[all …]
A Dedid.c94 port = PORT_C; in cnp_get_port_from_gmbus0()
110 port = PORT_C; in bxt_get_port_from_gmbus0()
124 port = PORT_C; in get_port_from_gmbus0()
A Dmmio.c285 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &= in intel_vgpu_reset_mmio()
287 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |= in intel_vgpu_reset_mmio()
A Dhandlers.c568 case PORT_C: in bxt_vgpu_get_dp_bitrate()
2372 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
2378 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2384 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); in init_generic_mmio_info()
2789 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL, in init_bxt_mmio_info()
/drivers/gpu/drm/i915/display/
A Dintel_display_device.c263 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C), /* DVO A/B/C */
272 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
282 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
292 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
307 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) /* SDVO B/C */
403 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */
415 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */
536 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* HDMI/DP B/C */
657 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* HDMI/DP B/C/D */
833 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C)
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A Dintel_dvo.c64 .port = PORT_C,
71 .port = PORT_C,
78 .port = PORT_C,
92 .port = PORT_C,
99 .port = PORT_C,
A Dintel_pch_display.c86 assert_pch_dp_disabled(display, pipe, PORT_C, PCH_DP_C); in assert_pch_ports_disabled()
101 assert_pch_hdmi_disabled(display, pipe, PORT_C, PCH_HDMIC); in assert_pch_ports_disabled()
170 ibx_sanitize_pch_dp_port(display, PORT_C, PCH_DP_C); in ibx_sanitize_pch_ports()
175 ibx_sanitize_pch_hdmi_port(display, PORT_C, PCH_HDMIC); in ibx_sanitize_pch_ports()
A Dintel_display_limits.h97 PORT_C, enumerator
A Dintel_dpio_phy.c177 [DPIO_CH1] = { .port = PORT_C },
219 [DPIO_CH0] = { .port = PORT_C },
668 case PORT_C: in vlv_dig_port_to_channel()
680 case PORT_C: in vlv_dig_port_to_phy()
1185 case PORT_C: in vlv_wait_port_ready()
A Dvlv_dsi.c309 if (intel_dsi->ports == BIT(PORT_C)) in intel_dsi_compute_config()
643 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { in intel_dsi_port_enable()
970 port == PORT_C) in intel_dsi_get_hw_state()
1432 MIPI_INIT_COUNT(display, port == PORT_A ? PORT_C : PORT_A), in intel_dsi_prepare()
1972 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); in vlv_dsi_init()
A Dg4x_hdmi.c661 return port == PORT_B || port == PORT_C; in is_hdmi_port_valid()
663 return port == PORT_B || port == PORT_C || port == PORT_D; in is_hdmi_port_valid()
A Dintel_hdmi.c2725 case PORT_C: in chv_encoder_to_ddc_pin()
2748 case PORT_C: in bxt_encoder_to_ddc_pin()
2768 case PORT_C: in cnp_encoder_to_ddc_pin()
2827 WARN_ON(encoder->port == PORT_C); in rkl_encoder_to_ddc_pin()
2869 WARN_ON(encoder->port == PORT_B || encoder->port == PORT_C); in adls_encoder_to_ddc_pin()
2890 case PORT_C: in g4x_encoder_to_ddc_pin()
A Dintel_dsi_vbt.c94 if (intel_dsi->ports & BIT(PORT_C)) in intel_dsi_seq_port_to_port()
95 return PORT_C; in intel_dsi_seq_port_to_port()
A Dintel_bios.c1654 enum port port_bc = DISPLAY_VER(display) >= 11 ? PORT_B : PORT_C; in parse_dsi_backlight_ports()
2350 [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, in dvo_port_to_port()
2365 [PORT_C] = { -1 }, in dvo_port_to_port()
2376 [PORT_C] = { -1 }, in dvo_port_to_port()
2385 [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, in dvo_port_to_port()
2426 return PORT_C; in dsi_dvo_port_to_port()
A Dintel_pipe_crc.c109 case PORT_C: in i9xx_pipe_crc_auto_source()
A Dintel_display.c1893 return TC_PORT_1 + port - PORT_C; in intel_port_to_tc()
3873 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { in bxt_get_dsi_transcoder_state()
7781 g4x_hdmi_init(display, PCH_HDMIC, PORT_C); in intel_setup_outputs()
7787 g4x_dp_init(display, PCH_DP_C, PORT_C); in intel_setup_outputs()
7819 has_edp = intel_dp_is_port_edp(display, PORT_C); in intel_setup_outputs()
7820 has_port = intel_bios_is_port_present(display, PORT_C); in intel_setup_outputs()
7822 has_edp &= g4x_dp_init(display, VLV_DP_C, PORT_C); in intel_setup_outputs()
7824 g4x_hdmi_init(display, VLV_HDMIC, PORT_C); in intel_setup_outputs()
7867 found = intel_sdvo_init(display, GEN3_SDVOC, PORT_C); in intel_setup_outputs()
7875 g4x_hdmi_init(display, GEN4_HDMIC, PORT_C); in intel_setup_outputs()
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A Dintel_ddi.c1931 case PORT_C: in bxt_ddi_get_pll()
3389 [PORT_C] = TRANSCODER_B, in gen9_chicken_trans_reg_by_port()
4949 if (port >= PORT_C) in icl_hpd_pin()
4950 return HPD_PORT_TC1 + port - PORT_C; in icl_hpd_pin()
4979 return port >= PORT_C; in intel_ddi_is_tc()
5032 case PORT_C: in port_strap_detected()
5183 port >= PORT_C ? " (TC)" : "", in intel_ddi_init()
A Dintel_display_power.c2393 .port_start = PORT_C,
2410 .port_end = PORT_C,
2437 .port_end = PORT_C,
A Dvlv_dsi_pll.c196 if (intel_dsi->ports & (1 << PORT_C)) in vlv_dsi_pll_compute()
A Dintel_display.h105 case PORT_C: in port_identifier()
A Dintel_pps.c1643 case PORT_C: in pps_init_registers()
1857 g4x_dp_port_enabled(display, PCH_DP_C, PORT_C, &panel_pipe); in assert_pps_unlocked()
A Dintel_hdcp.c470 case PORT_C: in intel_hdcp_get_repeater_ctl()
A Dintel_sdvo.c3368 return port == PORT_B || port == PORT_C; in is_sdvo_port_valid()
/drivers/gpu/drm/i915/
A Dintel_gvt_mmio_table.c499 MMIO_D(PORT_CLK_SEL(PORT_C)); in iterate_generic_mmio()
530 MMIO_D(DDI_BUF_CTL(PORT_C)); in iterate_generic_mmio()
535 MMIO_D(DP_TP_CTL(PORT_C)); in iterate_generic_mmio()
540 MMIO_D(DP_TP_STATUS(PORT_C)); in iterate_generic_mmio()
1142 MMIO_D(BXT_PHY_CTL(PORT_C)); in iterate_bxt_mmio()
1145 MMIO_D(BXT_PORT_PLL_ENABLE(PORT_C)); in iterate_bxt_mmio()
/drivers/staging/media/ipu7/
A Dipu7-isys-csi-phy.c28 #define PORT_C 2U macro
511 id == PORT_B || id == PORT_C) { in ipu7_isys_dphy_config()
553 if (!is_ipu7(isys->adev->isp->hw_ver) || id == PORT_B || id == PORT_C) in ipu7_isys_dphy_config()

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