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Searched refs:PORT_D (Results 1 – 22 of 22) sorted by relevance

/drivers/gpu/drm/i915/gvt/
A Ddisplay.c468 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) { in emulate_monitor_status_change()
470 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_D); in emulate_monitor_status_change()
472 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_D); in emulate_monitor_status_change()
474 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D); in emulate_monitor_status_change()
481 (PORT_D << TRANS_DDI_PORT_SHIFT) | in emulate_monitor_status_change()
484 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &= in emulate_monitor_status_change()
486 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |= in emulate_monitor_status_change()
489 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE; in emulate_monitor_status_change()
490 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE; in emulate_monitor_status_change()
783 clean_virtual_dp_monitor(vgpu, PORT_D); in intel_vgpu_clean_display()
[all …]
A Dedid.c96 port = PORT_D; in cnp_get_port_from_gmbus0()
112 port = PORT_D; in bxt_get_port_from_gmbus0()
128 port = PORT_D; in get_port_from_gmbus0()
A Dvgpu.c378 ret = intel_gvt_set_edid(vgpu, PORT_D); in intel_gvt_create_vgpu()
A Dhandlers.c671 if (port != PORT_B && port != PORT_D) { in vgpu_update_refresh_rate()
2373 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
2379 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2385 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); in init_generic_mmio_info()
/drivers/gpu/drm/i915/display/
A Dintel_display_limits.h98 PORT_D, enumerator
106 PORT_TC1 = PORT_D,
A Dintel_display_device.c426 ….__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D…
438 ….__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D…
453 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) /* DP A, SDV…
482 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SD…
585 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E…
638 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E…
657 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* HDMI/DP B/C/D */
682 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E…
931 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E…
939 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D),
[all …]
A Dintel_pch_display.c87 assert_pch_dp_disabled(display, pipe, PORT_D, PCH_DP_D); in assert_pch_ports_disabled()
102 assert_pch_hdmi_disabled(display, pipe, PORT_D, PCH_HDMID); in assert_pch_ports_disabled()
171 ibx_sanitize_pch_dp_port(display, PORT_D, PCH_DP_D); in ibx_sanitize_pch_ports()
176 ibx_sanitize_pch_hdmi_port(display, PORT_D, PCH_HDMID); in ibx_sanitize_pch_ports()
438 drm_WARN_ON(display->drm, port < PORT_B || port > PORT_D); in ilk_pch_enable()
A Dg4x_hdmi.c663 return port == PORT_B || port == PORT_C || port == PORT_D; in is_hdmi_port_valid()
752 if (port == PORT_D) in g4x_hdmi_init()
A Dintel_dpio_phy.c666 case PORT_D: in vlv_dig_port_to_channel()
682 case PORT_D: in vlv_dig_port_to_phy()
1190 case PORT_D: in vlv_wait_port_ready()
A Dintel_combo_phy.c166 bool ddi_d_present = intel_bios_is_port_present(display, PORT_D); in ehl_vbt_ddi_d_present()
A Dintel_pipe_crc.c112 case PORT_D: in i9xx_pipe_crc_auto_source()
A Dintel_display.h107 case PORT_D: in port_identifier()
A Dintel_display.c1878 port == PORT_D) in intel_port_to_phy()
7766 dpd_is_edp = intel_dp_is_port_edp(display, PORT_D); in intel_setup_outputs()
7784 g4x_hdmi_init(display, PCH_HDMID, PORT_D); in intel_setup_outputs()
7790 g4x_dp_init(display, PCH_DP_D, PORT_D); in intel_setup_outputs()
7831 has_port = intel_bios_is_port_present(display, PORT_D); in intel_setup_outputs()
7833 g4x_dp_init(display, CHV_DP_D, PORT_D); in intel_setup_outputs()
7835 g4x_hdmi_init(display, CHV_HDMID, PORT_D); in intel_setup_outputs()
7882 g4x_dp_init(display, DP_D, PORT_D); in intel_setup_outputs()
A Dintel_hdmi.c2728 case PORT_D: in chv_encoder_to_ddc_pin()
2771 case PORT_D: in cnp_encoder_to_ddc_pin()
2893 case PORT_D: in g4x_encoder_to_ddc_pin()
A Dintel_pps.c1646 case PORT_D: in pps_init_registers()
1860 g4x_dp_port_enabled(display, PCH_DP_D, PORT_D, &panel_pipe); in assert_pps_unlocked()
A Dintel_ddi.c3390 [PORT_D] = TRANSCODER_C, in gen9_chicken_trans_reg_by_port()
4957 if (port == PORT_D) in ehl_hpd_pin()
5034 case PORT_D: in port_strap_detected()
5164 port_name(port - PORT_D_XELPD + PORT_D), in intel_ddi_init()
A Dg4x_dp.c1376 if (port == PORT_D) in g4x_dp_init()
A Dintel_hdcp.c472 case PORT_D: in intel_hdcp_get_repeater_ctl()
A Dintel_bios.c2351 [PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, in dvo_port_to_port()
A Dintel_dpll_mgr.c3363 if (port == PORT_D || port == PORT_E) { in icl_get_combo_phy_dpll()
/drivers/gpu/drm/i915/
A Dintel_gvt_mmio_table.c500 MMIO_D(PORT_CLK_SEL(PORT_D)); in iterate_generic_mmio()
531 MMIO_D(DDI_BUF_CTL(PORT_D)); in iterate_generic_mmio()
536 MMIO_D(DP_TP_CTL(PORT_D)); in iterate_generic_mmio()
541 MMIO_D(DP_TP_STATUS(PORT_D)); in iterate_generic_mmio()
/drivers/staging/media/ipu7/
A Dipu7-isys-csi-phy.c29 #define PORT_D 3U macro

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