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Searched refs:PPI_RW_DDLCAL_CFG_2 (Results 1 – 2 of 2) sorted by relevance

/drivers/staging/media/ipu7/
A Dipu7-isys-csi-phy.c470 dwc_phy_write_mask(isys, id, PPI_RW_DDLCAL_CFG_2, 4, 12, 15); in ipu7_isys_dphy_config()
471 dwc_phy_write_mask(isys, id, PPI_RW_DDLCAL_CFG_2, 2, 10, 11); in ipu7_isys_dphy_config()
472 dwc_phy_write_mask(isys, id, PPI_RW_DDLCAL_CFG_2, 1, 8, 8); in ipu7_isys_dphy_config()
473 dwc_phy_write_mask(isys, id, PPI_RW_DDLCAL_CFG_2, 38, 0, 7); in ipu7_isys_dphy_config()
474 dwc_phy_write_mask(isys, id, PPI_RW_DDLCAL_CFG_2, 1, 9, 9); in ipu7_isys_dphy_config()
A Dipu7-isys-csi2-regs.h111 #define PPI_RW_DDLCAL_CFG_2 0x1c44 macro

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