Searched refs:PSEC_PER_SEC (Results 1 – 7 of 7) sorted by relevance
| /drivers/phy/ |
| A D | phy-core-mipi-dphy.c | 36 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); in phy_mipi_dphy_calc_config()
114 ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
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| /drivers/iio/trigger/ |
| A D | iio-trig-hrtimer.c | 20 #define PSEC_PER_SEC 1000000000000LL macro
73 period = PSEC_PER_SEC; in iio_hrtimer_store_sampling_frequency()
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| /drivers/gpu/drm/rockchip/ |
| A D | dw-mipi-dsi2-rockchip.c | 32 #define PSEC_PER_SEC 1000000000000LL macro
189 ui = ALIGN(PSEC_PER_SEC, hstx_clk); in dw_mipi_dsi2_phy_get_timing()
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| /drivers/phy/rockchip/ |
| A D | phy-rockchip-inno-dsidphy.c | 415 t_txbyteclkhs = div_u64(PSEC_PER_SEC, txbyteclkhs); in inno_dsidphy_mipi_mode_enable()
419 t_txclkesc = div_u64(PSEC_PER_SEC, txclkesc); in inno_dsidphy_mipi_mode_enable()
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| /drivers/dpll/zl3073x/ |
| A D | dpll.c | 580 conn_period = div_s64(PSEC_PER_SEC, conn_freq); in zl3073x_dpll_input_pin_phase_offset_get()
1421 phase_comp *= (int)div_u64(PSEC_PER_SEC, 2 * synth_freq); in zl3073x_dpll_output_pin_phase_adjust_get()
1455 half_synth_cycle = (int)div_u64(PSEC_PER_SEC, 2 * synth_freq); in zl3073x_dpll_output_pin_phase_adjust_set()
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| /drivers/net/ethernet/mscc/ |
| A D | ocelot_ptp.c | 155 adj = PSEC_PER_SEC << 16; in ocelot_ptp_adjfine()
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| /drivers/media/i2c/ |
| A D | tc358746.c | 580 return tc358746_cfg_to_cnt(cfg_val, clk_hz, PSEC_PER_SEC); in tc358746_ps_to_cnt()
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