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Searched refs:PixelClockBackEnd (Results 1 – 17 of 17) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddisplay_mode_vba_util_32.h259 double PixelClockBackEnd,
330 double PixelClockBackEnd,
A Ddisplay_mode_vba_util_32.c1346 double PixelClockBackEnd, in dml32_CalculateOutputLink() argument
1406 OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, in dml32_CalculateOutputLink()
1415 OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, in dml32_CalculateOutputLink()
1428 OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, in dml32_CalculateOutputLink()
1438 OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, in dml32_CalculateOutputLink()
1451 OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, in dml32_CalculateOutputLink()
1459 OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, in dml32_CalculateOutputLink()
1474 OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, in dml32_CalculateOutputLink()
1498 OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, in dml32_CalculateOutputLink()
1523 OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, in dml32_CalculateOutputLink()
[all …]
A Ddisplay_mode_vba_32.c348 v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 12 in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
352 v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 6 in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
356 v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 3 in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
370 mode_lib->vba.PixelClockBackEnd[k], mode_lib->vba.ip.dsc_delay_factor_wa); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2097 mode_lib->vba.PixelClockBackEnd[k], in dml32_ModeSupportAndSystemConfigurationFull()
2418 mode_lib->vba.PixelClockBackEnd[k], in dml32_ModeSupportAndSystemConfigurationFull()
2466 …if (mode_lib->vba.PixelClockBackEnd[k] / 12.0 / mode_lib->vba.DSCFormatFactor > (1.0 - mode_lib->v… in dml32_ModeSupportAndSystemConfigurationFull()
2470 …if (mode_lib->vba.PixelClockBackEnd[k] / 6.0 / mode_lib->vba.DSCFormatFactor > (1.0 - mode_lib->vb… in dml32_ModeSupportAndSystemConfigurationFull()
2473 …if (mode_lib->vba.PixelClockBackEnd[k] / 3.0 / mode_lib->vba.DSCFormatFactor > (1.0 - mode_lib->vb… in dml32_ModeSupportAndSystemConfigurationFull()
2528 mode_lib->vba.PixelClock[k], mode_lib->vba.PixelClockBackEnd[k], in dml32_ModeSupportAndSystemConfigurationFull()
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddisplay_mode_vba_20.c1784 mode_lib->vba.PixelClockBackEnd[k] / 6 in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1791 mode_lib->vba.PixelClockBackEnd[k] / 3 in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1836 / mode_lib->vba.PixelClockBackEnd[k]; in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4073 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20_ModeSupportAndSystemConfigurationFull()
4193 if (mode_lib->vba.PixelClockBackEnd[k] / 6.0 / mode_lib->vba.DSCFormatFactor in dml20_ModeSupportAndSystemConfigurationFull()
4199 if (mode_lib->vba.PixelClockBackEnd[k] / 3.0 / mode_lib->vba.DSCFormatFactor in dml20_ModeSupportAndSystemConfigurationFull()
4237 } else if (mode_lib->vba.PixelClockBackEnd[k] > 3200.0) { in dml20_ModeSupportAndSystemConfigurationFull()
4239 mode_lib->vba.PixelClockBackEnd[k] / 400.0, in dml20_ModeSupportAndSystemConfigurationFull()
4241 } else if (mode_lib->vba.PixelClockBackEnd[k] > 1360.0) { in dml20_ModeSupportAndSystemConfigurationFull()
4243 } else if (mode_lib->vba.PixelClockBackEnd[k] > 680.0) { in dml20_ModeSupportAndSystemConfigurationFull()
[all …]
A Ddisplay_mode_vba_20v2.c1820 mode_lib->vba.PixelClockBackEnd[k] / 6 in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1827 mode_lib->vba.PixelClockBackEnd[k] / 3 in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1872 / mode_lib->vba.PixelClockBackEnd[k]; in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4188 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20v2_ModeSupportAndSystemConfigurationFull()
4314 if (mode_lib->vba.PixelClockBackEnd[k] / 6.0 / mode_lib->vba.DSCFormatFactor in dml20v2_ModeSupportAndSystemConfigurationFull()
4320 if (mode_lib->vba.PixelClockBackEnd[k] / 3.0 / mode_lib->vba.DSCFormatFactor in dml20v2_ModeSupportAndSystemConfigurationFull()
4358 } else if (mode_lib->vba.PixelClockBackEnd[k] > 3200.0) { in dml20v2_ModeSupportAndSystemConfigurationFull()
4360 mode_lib->vba.PixelClockBackEnd[k] / 400.0, in dml20v2_ModeSupportAndSystemConfigurationFull()
4362 } else if (mode_lib->vba.PixelClockBackEnd[k] > 1360.0) { in dml20v2_ModeSupportAndSystemConfigurationFull()
4364 } else if (mode_lib->vba.PixelClockBackEnd[k] > 680.0) { in dml20v2_ModeSupportAndSystemConfigurationFull()
[all …]
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
A Ddml2_core_shared_types.h522 double PixelClockBackEnd[DML2_MAX_PLANES]; member
802 double PixelClockBackEnd[DML2_MAX_PLANES]; member
1031 double PixelClockBackEnd[DML2_MAX_PLANES]; member
1140 double PixelClockBackEnd[DML2_MAX_PLANES]; member
A Ddml2_core_dcn4_calcs.c4201 double PixelClockBackEnd, in CalculateOutputLink() argument
4233 DML_LOG_VERBOSE("DML::%s: PixelClockBackEnd = %f\n", __func__, PixelClockBackEnd); in CalculateOutputLink()
4486 double PixelClockBackEnd) in DSCDelayRequirement() argument
8361 if (s->PixelClockBackEnd[k] > 4800) { in dml_core_mode_support()
8363 } else if (s->PixelClockBackEnd[k] > 2400) { in dml_core_mode_support()
8365 } else if (s->PixelClockBackEnd[k] > 1200) { in dml_core_mode_support()
8367 } else if (s->PixelClockBackEnd[k] > 340) { in dml_core_mode_support()
8425 s->PixelClockBackEnd[k], in dml_core_mode_support()
8698 s->PixelClockBackEnd[k], in dml_core_mode_support()
8807 s->PixelClockBackEnd[k]); in dml_core_mode_support()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn21/
A Ddisplay_mode_vba_21.c1776 mode_lib->vba.PixelClockBackEnd[k] / 6 in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1783 mode_lib->vba.PixelClockBackEnd[k] / 3 in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1828 / mode_lib->vba.PixelClockBackEnd[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4282 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml21_ModeSupportAndSystemConfigurationFull()
4408 if (mode_lib->vba.PixelClockBackEnd[k] / 6.0 / mode_lib->vba.DSCFormatFactor in dml21_ModeSupportAndSystemConfigurationFull()
4414 if (mode_lib->vba.PixelClockBackEnd[k] / 3.0 / mode_lib->vba.DSCFormatFactor in dml21_ModeSupportAndSystemConfigurationFull()
4452 } else if (mode_lib->vba.PixelClockBackEnd[k] > 3200.0) { in dml21_ModeSupportAndSystemConfigurationFull()
4454 mode_lib->vba.PixelClockBackEnd[k] / 400.0, in dml21_ModeSupportAndSystemConfigurationFull()
4456 } else if (mode_lib->vba.PixelClockBackEnd[k] > 1360.0) { in dml21_ModeSupportAndSystemConfigurationFull()
4458 } else if (mode_lib->vba.PixelClockBackEnd[k] > 680.0) { in dml21_ModeSupportAndSystemConfigurationFull()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddisplay_mode_vba_31.c4270 if (v->PixelClockBackEnd[k] > 3200) {
4299 v->PixelClockBackEnd[k],
4336 v->PixelClockBackEnd[k],
4355 v->PixelClockBackEnd[k],
4378 v->PixelClockBackEnd[k],
4397 v->PixelClockBackEnd[k],
4420 v->PixelClockBackEnd[k],
4439 v->PixelClockBackEnd[k],
4462 v->PixelClockBackEnd[k],
4482 v->PixelClockBackEnd[k],
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn314/
A Ddisplay_mode_vba_314.c4357 if (v->PixelClockBackEnd[k] > 3200) {
4386 v->PixelClockBackEnd[k],
4423 v->PixelClockBackEnd[k],
4442 v->PixelClockBackEnd[k],
4465 v->PixelClockBackEnd[k],
4484 v->PixelClockBackEnd[k],
4507 v->PixelClockBackEnd[k],
4526 v->PixelClockBackEnd[k],
4549 v->PixelClockBackEnd[k],
4569 v->PixelClockBackEnd[k],
[all …]
/drivers/gpu/drm/amd/display/dc/dml2/
A Ddisplay_mode_core.c84 dml_float_t PixelClockBackEnd,
745 dml_float_t PixelClockBackEnd);
2699 display_cfg->output.PixelClockBackEnd[k] = display_cfg->timing.PixelClock[k]; in PixelClockAdjustmentForProgressiveToInterlaceUnit()
5351 dml_float_t PixelClockBackEnd, in CalculateOutputLink() argument
5881 dml_float_t PixelClockBackEnd) in DSCDelayRequirement() argument
5909 dml_print("DML::%s: PixelClockBackEnd = %f\n", __func__, PixelClockBackEnd); in DSCDelayRequirement()
6951 if (mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] > 4800) { in dml_core_mode_support()
7104 mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k], in dml_core_mode_support()
7371 mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k], in dml_core_mode_support()
7485 mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k]); in dml_core_mode_support()
[all …]
A Ddml2_utils.c124 dml_output_array->PixelClockBackEnd[dst_index] = dml_output_array->PixelClockBackEnd[src_index]; in dml2_util_copy_dml_output()
A Ddisplay_mode_core_structs.h627 dml_float_t PixelClockBackEnd[__DML_NUM_PLANES__]; member
A Ddml2_translation_helper.c884 out->PixelClockBackEnd[location] = in->timing.pix_clk_100hz / 10000.00; in populate_dml_output_cfg_from_stream_state()
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddisplay_mode_vba_30.c2112 v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 6 in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2115 v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 3 in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4026 if (v->PixelClockBackEnd[k] > 3200) { in dml30_ModeSupportAndSystemConfigurationFull()
4028 } else if (v->PixelClockBackEnd[k] > 1360) { in dml30_ModeSupportAndSystemConfigurationFull()
4030 } else if (v->PixelClockBackEnd[k] > 680) { in dml30_ModeSupportAndSystemConfigurationFull()
4032 } else if (v->PixelClockBackEnd[k] > 340) { in dml30_ModeSupportAndSystemConfigurationFull()
4055 v->PixelClockBackEnd[k], in dml30_ModeSupportAndSystemConfigurationFull()
4087 v->PixelClockBackEnd[k], in dml30_ModeSupportAndSystemConfigurationFull()
4107 v->PixelClockBackEnd[k], in dml30_ModeSupportAndSystemConfigurationFull()
4127 v->PixelClockBackEnd[k], in dml30_ModeSupportAndSystemConfigurationFull()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/
A Ddisplay_mode_vba.c706 mode_lib->vba.PixelClockBackEnd[mode_lib->vba.NumberOfActivePlanes] = dst->pixel_rate_mhz; in fetch_pipe_params()
1054 mode_lib->vba.PixelClockBackEnd[k] = mode_lib->vba.PixelClock[k]; in PixelClockAdjustmentForProgressiveToInterlaceUnit()
A Ddisplay_mode_vba.h477 double PixelClockBackEnd[DC__NUM_DPP__MAX]; member

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