| /drivers/infiniband/hw/hfi1/ |
| A D | trace.c | 263 case OP(RC, SEND_LAST_WITH_IMMEDIATE): in parse_everbs_hdrs()
265 case OP(RC, SEND_ONLY_WITH_IMMEDIATE): in parse_everbs_hdrs()
282 case OP(RC, RDMA_READ_REQUEST): in parse_everbs_hdrs()
283 case OP(RC, RDMA_WRITE_FIRST): in parse_everbs_hdrs()
285 case OP(RC, RDMA_WRITE_ONLY): in parse_everbs_hdrs()
293 case OP(RC, RDMA_READ_RESPONSE_LAST): in parse_everbs_hdrs()
294 case OP(RC, RDMA_READ_RESPONSE_ONLY): in parse_everbs_hdrs()
295 case OP(RC, ACKNOWLEDGE): in parse_everbs_hdrs()
394 case OP(RC, ATOMIC_ACKNOWLEDGE): in parse_everbs_hdrs()
402 case OP(RC, COMPARE_SWAP): in parse_everbs_hdrs()
[all …]
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| /drivers/media/cec/ |
| A D | Kconfig | 14 bool "HDMI CEC RC integration"
18 Pass on CEC remote control messages to the RC framework.
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| /drivers/clocksource/ |
| A D | timer-atmel-tcb.c | 80 tcb_cache[i].rc = readl(tcaddr + ATMEL_TC_REG(i, RC)); in tc_clksrc_suspend()
95 writel(tcb_cache[i].rc, tcaddr + ATMEL_TC_REG(i, RC)); in tc_clksrc_resume()
208 writel((tcd->rate + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC)); in tc_set_periodic()
221 writel_relaxed(delta, tcaddr + ATMEL_TC_REG(2, RC)); in tc_next_event()
323 writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC)); in tcb_setup_dual_chan()
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| /drivers/pci/controller/dwc/ |
| A D | Kconfig | 131 This controller can work either as EP or RC. The RCW[HOST_AGT_PEX]
133 controller works in RC mode.
143 This controller can work either as EP or RC. The RCW[HOST_AGT_PEX]
145 controller works in RC mode.
238 Tegra194. This controller can work either as EP or RC. In order to
253 Tegra194. This controller can work either as EP or RC. In order to
270 This controller can work either as EP or RC. In order to enable
285 This controller can work either as EP or RC. In order to enable
439 This controller can work either as EP or RC. In order to enable
454 This controller can work either as EP or RC. In order to enable
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| A D | pci-keystone.c | 101 #define RC 0x2 macro
1050 val = KS_PCIE_DEV_TYPE(RC) | KS_PCIE_SYSCLOCKOUTEN; in ks_pcie_set_mode()
1085 val = RC; in ks_pcie_am654_set_mode()
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| /drivers/pwm/ |
| A D | pwm-atmel-tcb.c | 102 regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC), in atmel_tcb_pwm_request()
248 regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC), in atmel_tcb_pwm_enable()
495 regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(channel, RC), &chan->rc); in atmel_tcb_pwm_suspend()
510 regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(channel, RC), chan->rc); in atmel_tcb_pwm_resume()
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| A D | dcn30_afmt.c | 102 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC; in speakers_to_channels()
104 cea_channels.channels.RL_RC = speaker_flags.RC; in speakers_to_channels()
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| /drivers/media/rc/ |
| A D | Kconfig | 80 tristate "Enable IR raw decoder for the RC-5 protocol"
84 Enable this option if you have IR with RC-5 protocol, and
96 tristate "Enable IR raw decoder for the RC-MM protocol"
98 Enable this option when you have IR with RC-MM protocol, and
100 24 and 32 bits RC-MM variants. You can enable or disable the
101 different modes using the following RC protocol keywords:
213 spaces, which is not enough for the NEC, Sanyo and RC-6 protocol.
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| /drivers/media/rc/keymaps/ |
| A D | Kconfig | 14 provide the tool and the same RC maps for load from
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| /drivers/input/joystick/ |
| A D | Kconfig | 211 tristate "5-byte Zhenhua RC transmitter"
324 tristate "Walkera WK-0701 RC transmitter"
387 tristate "FlySky FS-iA6B RC Receiver"
390 Say Y here if you use a FlySky FS-i6 RC remote control along with the
391 FS-iA6B RC receiver as a joystick input device.
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| /drivers/pci/endpoint/ |
| A D | Kconfig | 36 doorbell. The RC can trigger doorbell in EP by writing data to a
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| /drivers/staging/media/ |
| A D | Kconfig | 8 Most of them don't follow properly the V4L, DVB and/or RC API's,
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| /drivers/counter/ |
| A D | microchip-tcb-capture.c | 312 ret = regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], RC), &cnt); in mchp_tc_count_compare_read()
329 return regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], RC), val); in mchp_tc_count_compare_write()
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| /drivers/dma/ |
| A D | hisi_dma.c | 97 RC, enumerator
804 writel_relaxed(mode == RC ? 1 : 0, in hisi_dma_set_mode()
1009 hisi_dma_set_mode(hdma_dev, RC); in hisi_dma_probe()
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| /drivers/nfc/ |
| A D | Kconfig | 48 RC-S380 dongle.
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| /drivers/infiniband/hw/mthca/ |
| A D | mthca_qp.c | 285 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS }; enumerator
290 case RC: return MTHCA_QP_ST_RC; in to_mthca_st()
476 if (qp->transport == RC || qp->transport == UC) { in mthca_query_qp()
1024 case RC: in mthca_alloc_wqe_buf()
1304 case IB_QPT_RC: qp->transport = RC; break; in mthca_alloc_qp()
1686 case RC: in mthca_tavor_post_send()
2016 case RC: in mthca_arbel_post_send()
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| /drivers/infiniband/core/ |
| A D | cma_trace.h | 144 ib_qp_type(RC) \
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| /drivers/gpu/drm/amd/display/dc/dio/dcn10/ |
| A D | dcn10_stream_encoder.c | 1146 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC; in speakers_to_channels()
1148 cea_channels.channels.RL_RC = speaker_flags.RC; in speakers_to_channels()
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_stream_encoder.c | 1133 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC; in speakers_to_channels()
1135 cea_channels.channels.RL_RC = speaker_flags.RC; in speakers_to_channels()
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| /drivers/gpu/drm/amd/display/dc/ |
| A D | dc_types.h | 456 uint32_t RC:1; member
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| /drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| A D | ramnv50.c | 109 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); in nv50_ram_timing_calc()
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| A D | ramgt215.c | 374 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); in gt215_ram_timing_calc()
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| /drivers/char/ |
| A D | Kconfig | 207 manufactured by RC Systems (<https://www.rcsys.com/>). It is also
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| /drivers/hid/ |
| A D | Kconfig | 964 bool "CIR via RC class" if EXPERT
|