| /drivers/gpu/drm/amd/display/dc/dccg/dcn314/ |
| A D | dcn314_dccg.c | 162 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
171 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
180 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
189 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
264 DPSTREAMCLK0_EN, (src == REFCLK) ? 0 : 1, in dccg314_set_dpstreamclk()
269 DPSTREAMCLK1_EN, (src == REFCLK) ? 0 : 1, in dccg314_set_dpstreamclk()
274 DPSTREAMCLK2_EN, (src == REFCLK) ? 0 : 1, in dccg314_set_dpstreamclk()
279 DPSTREAMCLK3_EN, (src == REFCLK) ? 0 : 1, in dccg314_set_dpstreamclk()
305 dccg314_set_dpstreamclk(dccg, REFCLK, otg_inst, in dccg314_init()
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| /drivers/gpu/drm/amd/display/dc/dccg/dcn32/ |
| A D | dcn32_dccg.c | 161 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
170 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
179 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
188 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
292 (src == REFCLK) ? 0 : 1, DPSTREAMCLK0_SRC_SEL, otg_inst); in dccg32_set_dpstreamclk()
296 (src == REFCLK) ? 0 : 1, DPSTREAMCLK1_SRC_SEL, otg_inst); in dccg32_set_dpstreamclk()
300 (src == REFCLK) ? 0 : 1, DPSTREAMCLK2_SRC_SEL, otg_inst); in dccg32_set_dpstreamclk()
304 (src == REFCLK) ? 0 : 1, DPSTREAMCLK3_SRC_SEL, otg_inst); in dccg32_set_dpstreamclk()
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| /drivers/clk/berlin/ |
| A D | bg2.c | 90 REFCLK, VIDEO_EXT0, enumerator
103 [REFCLK] = "refclk",
516 clk = of_clk_get_by_name(np, clk_names[REFCLK]); in berlin2_clock_setup()
518 clk_names[REFCLK] = __clk_get_name(clk); in berlin2_clock_setup()
530 clk_names[SYSPLL], clk_names[REFCLK], 0); in berlin2_clock_setup()
535 clk_names[MEMPLL], clk_names[REFCLK], 0); in berlin2_clock_setup()
540 clk_names[CPUPLL], clk_names[REFCLK], 0); in berlin2_clock_setup()
549 clk_names[REFCLK], avpll_flags, 0); in berlin2_clock_setup()
577 parent_names[1] = clk_names[REFCLK]; in berlin2_clock_setup()
585 parent_names[1] = clk_names[REFCLK]; in berlin2_clock_setup()
[all …]
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| A D | bg2q.c | 45 REFCLK, enumerator
52 [REFCLK] = "refclk",
313 clk = of_clk_get_by_name(np, clk_names[REFCLK]); in berlin2q_clock_setup()
315 clk_names[REFCLK] = __clk_get_name(clk); in berlin2q_clock_setup()
321 clk_names[SYSPLL], clk_names[REFCLK], 0); in berlin2q_clock_setup()
326 clk_names[CPUPLL], clk_names[REFCLK], 0); in berlin2q_clock_setup()
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| /drivers/gpu/drm/amd/display/dc/dccg/dcn35/ |
| A D | dcn35_dccg.c | 1312 if (src == REFCLK) in dccg35_set_dtbclk_p_src()
1321 if (src == REFCLK) in dccg35_set_dtbclk_p_src()
1330 if (src == REFCLK) in dccg35_set_dtbclk_p_src()
1339 if (src == REFCLK) in dccg35_set_dtbclk_p_src()
1447 (src == REFCLK) ? 0 : 1, DPSTREAMCLK0_SRC_SEL, otg_inst); in dccg35_set_dpstreamclk()
1449 REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_ROOT_GATE_DISABLE, (src == REFCLK) ? 0 : 1); in dccg35_set_dpstreamclk()
1453 (src == REFCLK) ? 0 : 1, DPSTREAMCLK1_SRC_SEL, otg_inst); in dccg35_set_dpstreamclk()
1459 (src == REFCLK) ? 0 : 1, DPSTREAMCLK2_SRC_SEL, otg_inst); in dccg35_set_dpstreamclk()
1465 (src == REFCLK) ? 0 : 1, DPSTREAMCLK3_SRC_SEL, otg_inst); in dccg35_set_dpstreamclk()
1760 dccg35_set_dpstreamclk(dccg, REFCLK, otg_inst, in dccg35_init()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dccg/dcn401/ |
| A D | dcn401_dccg.c | 225 if (src == REFCLK) in dccg401_set_dtbclk_p_src()
234 if (src == REFCLK) in dccg401_set_dtbclk_p_src()
243 if (src == REFCLK) in dccg401_set_dtbclk_p_src()
252 if (src == REFCLK) in dccg401_set_dtbclk_p_src()
584 if (src == REFCLK) in dccg401_set_dpstreamclk()
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| /drivers/clk/versatile/ |
| A D | Kconfig | 19 Supports clock muxing (REFCLK/TIMCLK to TIMERCLKEN0-3) capabilities
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | dccg.h | 49 REFCLK, // Selects REFCLK as source for hdmistreamclk. enumerator
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| /drivers/video/fbdev/savage/ |
| A D | savagefb.h | 210 int MCLK, REFCLK, LCDclk; member
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| /drivers/gpu/drm/amd/display/dc/dccg/dcn31/ |
| A D | dcn31_dccg.c | 167 if (src == REFCLK) in dccg31_set_dpstreamclk()
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| /drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| A D | dce110_hwseq.c | 1188 dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst); in dce110_disable_stream()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| A D | dcn401_hwseq.c | 1857 …dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, REFCLK, pipe_ctx->stream_res.tg->i… in dcn401_reset_back_end_for_pipe()
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