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Searched refs:REG (Results 1 – 25 of 272) sorted by relevance

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/drivers/net/ethernet/mscc/
A Dvsc7514_regs.c154 REG(QS_XTR_RD, 0x000008),
160 REG(QS_INJ_WR, 0x00002c),
222 REG(REW_PPT, 0x000680),
383 REG(DEV_CLOCK_CFG, 0x0),
384 REG(DEV_PORT_MISC, 0x4),
385 REG(DEV_EVENTS, 0x8),
386 REG(DEV_EEE_CFG, 0xc),
401 REG(PCS1G_CFG, 0x48),
403 REG(PCS1G_SD_CFG, 0x50),
406 REG(PCS1G_LB_CFG, 0x5c),
[all …]
/drivers/net/dsa/ocelot/
A Dseville_vsc9953.c43 REG(ANA_ADVLEARN, 0x00b500),
44 REG(ANA_VLANMASK, 0x00b504),
46 REG(ANA_ANAGEFIL, 0x00b50c),
47 REG(ANA_ANEVENTS, 0x00b510),
52 REG(ANA_AUTOAGE, 0x00b530),
55 REG(ANA_AGENCTRL, 0x00b53c),
58 REG(ANA_FLOODING, 0x00b548),
146 REG(QS_XTR_RD, 0x000008),
407 REG(DEV_CLOCK_CFG, 0x0),
408 REG(DEV_PORT_MISC, 0x4),
[all …]
A Dfelix_vsc9959.c49 REG(ANA_ADVLEARN, 0x0089a0),
50 REG(ANA_VLANMASK, 0x0089a4),
52 REG(ANA_ANAGEFIL, 0x0089ac),
53 REG(ANA_ANEVENTS, 0x0089b0),
58 REG(ANA_AUTOAGE, 0x0089d0),
61 REG(ANA_AGENCTRL, 0x0089dc),
64 REG(ANA_FLOODING, 0x0089e8),
463 REG(DEV_CLOCK_CFG, 0x0),
464 REG(DEV_PORT_MISC, 0x4),
465 REG(DEV_EVENTS, 0x8),
[all …]
/drivers/net/ethernet/apple/
A Dmace.h12 REG(rcvfifo); /* receive FIFO */
13 REG(xmtfifo); /* transmit FIFO */
22 REG(pr); /* poll register */
31 REG(reg19);
34 REG(reg22);
35 REG(reg23);
37 REG(reg25);
40 REG(reg28);
41 REG(utr); /* user test reg */
42 REG(reg30);
[all …]
/drivers/gpu/drm/i915/gt/
A Dintel_lrc.c110 REG(0x034),
111 REG(0x030),
112 REG(0x038),
113 REG(0x03c),
114 REG(0x168),
115 REG(0x140),
116 REG(0x110),
117 REG(0x11c),
118 REG(0x114),
119 REG(0x118),
[all …]
/drivers/regulator/
A Drn5t618-regulator.c25 #define REG(rid, ereg, emask, vreg, vmask, min, max, step) \ macro
45 REG(DCDC1, DC1CTL, BIT(0), DC1DAC, 0xff, 600000, 3500000, 12500),
46 REG(DCDC2, DC2CTL, BIT(0), DC2DAC, 0xff, 600000, 3500000, 12500),
47 REG(DCDC3, DC3CTL, BIT(0), DC3DAC, 0xff, 600000, 3500000, 12500),
48 REG(DCDC4, DC4CTL, BIT(0), DC4DAC, 0xff, 600000, 3500000, 12500),
50 REG(LDO1, LDOEN1, BIT(0), LDO1DAC, 0x7f, 900000, 3500000, 25000),
51 REG(LDO2, LDOEN1, BIT(1), LDO2DAC, 0x7f, 900000, 3500000, 25000),
52 REG(LDO3, LDOEN1, BIT(2), LDO3DAC, 0x7f, 600000, 3500000, 25000),
53 REG(LDO4, LDOEN1, BIT(3), LDO4DAC, 0x7f, 900000, 3500000, 25000),
54 REG(LDO5, LDOEN1, BIT(4), LDO5DAC, 0x7f, 900000, 3500000, 25000),
[all …]
/drivers/gpu/drm/amd/display/dc/gpio/dce120/
A Dhw_translate_dce120.c51 #define REG(reg_name)\ macro
99 case REG(DC_GPIO_HPD_A): in offset_to_id()
126 case REG(DC_GPIO_SYNCA_A): in offset_to_id()
141 case REG(DC_GPIO_GENLK_A): in offset_to_id()
165 case REG(DC_GPIO_DDC1_A): in offset_to_id()
168 case REG(DC_GPIO_DDC2_A): in offset_to_id()
171 case REG(DC_GPIO_DDC3_A): in offset_to_id()
174 case REG(DC_GPIO_DDC4_A): in offset_to_id()
177 case REG(DC_GPIO_DDC5_A): in offset_to_id()
180 case REG(DC_GPIO_DDC6_A): in offset_to_id()
[all …]
/drivers/gpu/drm/amd/display/dc/gpio/dcn10/
A Dhw_translate_dcn10.c51 #define REG(reg_name)\ macro
99 case REG(DC_GPIO_HPD_A): in offset_to_id()
126 case REG(DC_GPIO_SYNCA_A): in offset_to_id()
141 case REG(DC_GPIO_GENLK_A): in offset_to_id()
165 case REG(DC_GPIO_DDC1_A): in offset_to_id()
168 case REG(DC_GPIO_DDC2_A): in offset_to_id()
171 case REG(DC_GPIO_DDC3_A): in offset_to_id()
174 case REG(DC_GPIO_DDC4_A): in offset_to_id()
177 case REG(DC_GPIO_DDC5_A): in offset_to_id()
180 case REG(DC_GPIO_DDC6_A): in offset_to_id()
[all …]
/drivers/gpu/drm/tidss/
A Dtidss_dispc_regs.h55 #define REG(r) (dispc_common_regmap[r ## _OFF]) macro
57 #define DSS_REVISION REG(DSS_REVISION)
58 #define DSS_SYSCONFIG REG(DSS_SYSCONFIG)
59 #define DSS_SYSSTATUS REG(DSS_SYSSTATUS)
60 #define DISPC_IRQ_EOI REG(DISPC_IRQ_EOI)
62 #define DISPC_IRQSTATUS REG(DISPC_IRQSTATUS)
69 #define WB_IRQENABLE REG(WB_IRQENABLE)
70 #define WB_IRQSTATUS REG(WB_IRQSTATUS)
75 #define DSS_CBA_CFG REG(DSS_CBA_CFG)
91 #define DISPC_MSS_VP1 REG(DISPC_MSS_VP1)
[all …]
/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
A Ddcn10_dpp_cm.c42 #define REG(reg)\ macro
135 gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12); in program_gamut_remap()
136 gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34); in program_gamut_remap()
145 gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12); in program_gamut_remap()
146 gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34); in program_gamut_remap()
213 gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12); in read_gamut_remap()
214 gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34); in read_gamut_remap()
223 gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12); in read_gamut_remap()
224 gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34); in read_gamut_remap()
288 gam_regs.csc_c11_c12 = REG(CM_OCSC_C11_C12); in dpp1_cm_program_color_matrix()
[all …]
/drivers/gpu/drm/amd/display/dc/dwb/dcn30/
A Ddcn30_dwb_cm.c36 #define REG(reg)\ macro
104 gam_regs.offset_b = REG(DWB_OGAM_RAMA_OFFSET_B); in dwb3_program_ogam_luta_settings()
105 gam_regs.offset_g = REG(DWB_OGAM_RAMA_OFFSET_G); in dwb3_program_ogam_luta_settings()
106 gam_regs.offset_r = REG(DWB_OGAM_RAMA_OFFSET_R); in dwb3_program_ogam_luta_settings()
107 gam_regs.region_start = REG(DWB_OGAM_RAMA_REGION_0_1); in dwb3_program_ogam_luta_settings()
108 gam_regs.region_end = REG(DWB_OGAM_RAMA_REGION_32_33); in dwb3_program_ogam_luta_settings()
137 gam_regs.offset_b = REG(DWB_OGAM_RAMB_OFFSET_B); in dwb3_program_ogam_lutb_settings()
138 gam_regs.offset_g = REG(DWB_OGAM_RAMB_OFFSET_G); in dwb3_program_ogam_lutb_settings()
139 gam_regs.offset_r = REG(DWB_OGAM_RAMB_OFFSET_R); in dwb3_program_ogam_lutb_settings()
140 gam_regs.region_start = REG(DWB_OGAM_RAMB_REGION_0_1); in dwb3_program_ogam_lutb_settings()
[all …]
/drivers/gpu/drm/amd/display/dc/gpio/dcn20/
A Dhw_translate_dcn20.c54 #undef REG
55 #define REG(reg_name)\ macro
73 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
103 case REG(DC_GPIO_HPD_A): in offset_to_id()
130 case REG(DC_GPIO_GENLK_A): in offset_to_id()
155 case REG(DC_GPIO_DDC1_A): in offset_to_id()
158 case REG(DC_GPIO_DDC2_A): in offset_to_id()
161 case REG(DC_GPIO_DDC3_A): in offset_to_id()
164 case REG(DC_GPIO_DDC4_A): in offset_to_id()
167 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
/drivers/gpu/drm/amd/display/dc/gpio/dcn30/
A Dhw_translate_dcn30.c59 #undef REG
60 #define REG(reg_name)\ macro
78 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
108 case REG(DC_GPIO_HPD_A): in offset_to_id()
135 case REG(DC_GPIO_GENLK_A): in offset_to_id()
160 case REG(DC_GPIO_DDC1_A): in offset_to_id()
163 case REG(DC_GPIO_DDC2_A): in offset_to_id()
166 case REG(DC_GPIO_DDC3_A): in offset_to_id()
169 case REG(DC_GPIO_DDC4_A): in offset_to_id()
172 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
A Ddcn30_dpp_cm.c33 #define REG(reg)\ macro
259 gam_regs.offset_b = REG(CM_GAMCOR_RAMB_OFFSET_B); in dpp3_program_gamcor_lut()
260 gam_regs.offset_g = REG(CM_GAMCOR_RAMB_OFFSET_G); in dpp3_program_gamcor_lut()
261 gam_regs.offset_r = REG(CM_GAMCOR_RAMB_OFFSET_R); in dpp3_program_gamcor_lut()
281 gam_regs.offset_b = REG(CM_GAMCOR_RAMA_OFFSET_B); in dpp3_program_gamcor_lut()
282 gam_regs.offset_g = REG(CM_GAMCOR_RAMA_OFFSET_G); in dpp3_program_gamcor_lut()
283 gam_regs.offset_r = REG(CM_GAMCOR_RAMA_OFFSET_R); in dpp3_program_gamcor_lut()
348 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12); in program_gamut_remap()
349 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34); in program_gamut_remap()
427 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12); in read_gamut_remap()
[all …]
/drivers/gpu/drm/amd/display/dc/gpio/dcn32/
A Dhw_translate_dcn32.c52 #undef REG
53 #define REG(reg_name)\ macro
71 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
98 case REG(DC_GPIO_HPD_A): in offset_to_id()
122 case REG(DC_GPIO_GENLK_A): in offset_to_id()
146 case REG(DC_GPIO_DDC1_A): in offset_to_id()
149 case REG(DC_GPIO_DDC2_A): in offset_to_id()
152 case REG(DC_GPIO_DDC3_A): in offset_to_id()
155 case REG(DC_GPIO_DDC4_A): in offset_to_id()
158 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
/drivers/gpu/drm/amd/display/dc/gpio/dcn21/
A Dhw_translate_dcn21.c54 #undef REG
55 #define REG(reg_name)\ macro
72 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
102 case REG(DC_GPIO_HPD_A): in offset_to_id()
129 case REG(DC_GPIO_GENLK_A): in offset_to_id()
154 case REG(DC_GPIO_DDC1_A): in offset_to_id()
157 case REG(DC_GPIO_DDC2_A): in offset_to_id()
160 case REG(DC_GPIO_DDC3_A): in offset_to_id()
163 case REG(DC_GPIO_DDC4_A): in offset_to_id()
166 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
/drivers/gpu/drm/amd/display/dc/gpio/dcn315/
A Dhw_translate_dcn315.c54 #undef REG
55 #define REG(reg_name)\ macro
73 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
103 case REG(DC_GPIO_HPD_A): in offset_to_id()
130 case REG(DC_GPIO_GENLK_A): in offset_to_id()
155 case REG(DC_GPIO_DDC1_A): in offset_to_id()
158 case REG(DC_GPIO_DDC2_A): in offset_to_id()
161 case REG(DC_GPIO_DDC3_A): in offset_to_id()
164 case REG(DC_GPIO_DDC4_A): in offset_to_id()
167 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
/drivers/gpu/drm/amd/display/dc/gpio/dcn401/
A Dhw_translate_dcn401.c27 #undef REG
28 #define REG(reg_name)\ macro
46 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
73 case REG(DC_GPIO_HPD_A): in offset_to_id()
97 case REG(DC_GPIO_GENLK_A): in offset_to_id()
122 case REG(DC_GPIO_DDC1_A): in offset_to_id()
125 case REG(DC_GPIO_DDC2_A): in offset_to_id()
128 case REG(DC_GPIO_DDC3_A): in offset_to_id()
131 case REG(DC_GPIO_DDC4_A): in offset_to_id()
134 case REG(DC_GPIO_DDCVGA_A): in offset_to_id()
[all …]
/drivers/accel/ivpu/
A Divpu_hw_reg_io.h32 #define REG_FLD(REG, FLD) \ argument
33 (REG##_##FLD##_MASK)
34 #define REG_FLD_NUM(REG, FLD, num) \ argument
35 FIELD_PREP(REG##_##FLD##_MASK, num)
36 #define REG_GET_FLD(REG, FLD, val) \ argument
37 FIELD_GET(REG##_##FLD##_MASK, val)
38 #define REG_CLR_FLD(REG, FLD, val) \ argument
39 ((val) & ~(REG##_##FLD##_MASK))
41 ((val) | (REG##_##FLD##_MASK))
43 (((val) & ~(REG##_##FLD##_MASK)) | FIELD_PREP(REG##_##FLD##_MASK, num))
[all …]
/drivers/gpu/drm/bridge/
A Dtda998x_drv.c105 #define REG(page, addr) (((page) << 8) | (addr)) macro
113 #define REG_VERSION_LSB REG(0x00, 0x00) /* read */
121 #define REG_VERSION_MSB REG(0x00, 0x02) /* read */
122 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */
144 #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
149 #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
154 #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
159 #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
168 #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
175 #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
[all …]
/drivers/gpu/drm/xe/
A Dxe_lrc.c201 REG(0x034),
202 REG(0x030),
203 REG(0x038),
204 REG(0x03c),
205 REG(0x168),
206 REG(0x140),
207 REG(0x110),
208 REG(0x1c0),
209 REG(0x1c4),
210 REG(0x1c8),
[all …]
/drivers/net/ipa/reg/
A Dgsi_reg-v3.1.c13 REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
16 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
176 REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP);
180 REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP);
184 REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
187 REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
190 REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
193 REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
198 REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
201 REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
[all …]
A Dgsi_reg-v3.5.1.c13 REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
16 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
187 REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP);
191 REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP);
195 REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
198 REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
201 REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
204 REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
209 REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
212 REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
[all …]
A Dgsi_reg-v4.0.c13 REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
16 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
192 REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP);
196 REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP);
200 REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
203 REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
206 REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
209 REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
214 REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
217 REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
[all …]
/drivers/gpu/drm/amd/display/dc/mpc/dcn20/
A Ddcn20_mpc.c33 #define REG(reg)\ macro
170 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]); in mpc2_set_output_csc()
171 ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]); in mpc2_set_output_csc()
173 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]); in mpc2_set_output_csc()
174 ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]); in mpc2_set_output_csc()
229 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]); in mpc2_set_ocsc_default()
230 ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]); in mpc2_set_ocsc_default()
232 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]); in mpc2_set_ocsc_default()
233 ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]); in mpc2_set_ocsc_default()
342 gam_regs.region_start = REG(MPCC_OGAM_RAMB_REGION_0_1[mpcc_id]); in mpc2_program_lutb()
[all …]

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