| /drivers/media/i2c/ |
| A D | ar0521.c | 681 REGS(be(0x301E), be(0x00AA)),
684 REGS(be(0x3042),
688 REGS(be(0x30D2),
694 REGS(be(0x30DA),
707 REGS(be(0x31B0),
722 REGS(be(0x3D00),
781 REGS(be(0x3EBA),
785 REGS(be(0x3EC0),
806 REGS(be(0x3F00),
819 REGS(be(0x3F10),
[all …]
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| A D | imx258.c | 531 #define REGS(_list) { .num_of_regs = ARRAY_SIZE(_list), .regs = _list, } macro
540 .reg_list = REGS(mipi_1267mbps_19_2mhz_2l),
544 .reg_list = REGS(mipi_1267mbps_19_2mhz_4l),
553 .reg_list = REGS(mipi_640mbps_19_2mhz_2l),
557 .reg_list = REGS(mipi_640mbps_19_2mhz_4l),
569 .reg_list = REGS(mipi_1272mbps_24mhz_2l),
573 .reg_list = REGS(mipi_1272mbps_24mhz_4l),
582 .reg_list = REGS(mipi_642mbps_24mhz_2l),
586 .reg_list = REGS(mipi_642mbps_24mhz_4l),
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| /drivers/video/fbdev/nvidia/ |
| A D | nv_setup.c | 295 par->PRAMIN = par->REGS + (0x00710000 / 4); in NVCommonSetup()
296 par->PCRTC0 = par->REGS + (0x00600000 / 4); in NVCommonSetup()
297 par->PRAMDAC0 = par->REGS + (0x00680000 / 4); in NVCommonSetup()
298 par->PFB = par->REGS + (0x00100000 / 4); in NVCommonSetup()
299 par->PFIFO = par->REGS + (0x00002000 / 4); in NVCommonSetup()
300 par->PGRAPH = par->REGS + (0x00400000 / 4); in NVCommonSetup()
301 par->PEXTDEV = par->REGS + (0x00101000 / 4); in NVCommonSetup()
302 par->PTIMER = par->REGS + (0x00009000 / 4); in NVCommonSetup()
303 par->PMC = par->REGS + (0x00000000 / 4); in NVCommonSetup()
304 par->FIFO = par->REGS + (0x00800000 / 4); in NVCommonSetup()
[all …]
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| A D | nvidia.c | 1205 volatile u32 __iomem *REGS) in nvidia_get_chipset() argument
1214 id = NV_RD32(REGS, 0x1800); in nvidia_get_chipset()
1284 volatile u32 __iomem *REGS; in nvidiafb_probe() local
1304 REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len); in nvidiafb_probe()
1305 if (!REGS) { in nvidiafb_probe()
1310 Chipset = nvidia_get_chipset(pd, REGS); in nvidiafb_probe()
1349 par->REGS = REGS; in nvidiafb_probe()
1433 iounmap(REGS); in nvidiafb_probe()
1451 iounmap(par->REGS); in nvidiafb_remove()
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| A D | nv_type.h | 155 volatile u32 __iomem *REGS; member
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| /drivers/gpu/drm/msm/adreno/ |
| A D | a6xx_gpu_state.h | 299 #define REGS(_array, _sel_reg, _sel_val) \ macro
304 REGS(a6xx_registers, 0, 0),
305 REGS(a660_registers, 0, 0),
306 REGS(a6xx_rb_rac_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0),
307 REGS(a6xx_rb_rbp_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 9),
336 REGS(a6xx_ahb_registers, 0, 0);
339 REGS(a6xx_vbif_registers, 0, 0);
342 REGS(a6xx_gbif_registers, 0, 0);
398 REGS(a6xx_gmu_cx_registers, 0, 0),
399 REGS(a6xx_gmu_cx_rscc_registers, 0, 0),
[all …]
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| /drivers/gpu/drm/amd/display/dmub/src/ |
| A D | dmub_reg.h | 43 #define REG(reg) (REGS)->offset.reg
45 #define FD(reg_field) (REGS)->shift.reg_field, (REGS)->mask.reg_field
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| A D | dmub_dcn301.c | 36 #define REGS dmub->regs macro
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| A D | dmub_dcn302.c | 36 #define REGS dmub->regs macro
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| A D | dmub_dcn303.c | 37 #define REGS dmub->regs macro
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| A D | dmub_dcn21.c | 36 #define REGS dmub->regs macro
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| A D | dmub_dcn315.c | 42 #define REGS dmub->regs_dcn31 macro
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| A D | dmub_dcn316.c | 42 #define REGS dmub->regs_dcn31 macro
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| A D | dmub_dcn314.c | 42 #define REGS dmub->regs_dcn31 macro
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| A D | dmub_dcn351.c | 13 #define REGS dmub->regs_dcn35 macro
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| A D | dmub_dcn36.c | 13 #define REGS dmub->regs_dcn35 macro
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| A D | dmub_dcn30.c | 37 #define REGS dmub->regs macro
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| A D | dmub_dcn20.c | 37 #define REGS dmub->regs macro
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| A D | dmub_dcn31.c | 36 #define REGS dmub->regs_dcn31 macro
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| A D | dmub_dcn35.c | 37 #define REGS dmub->regs_dcn35 macro
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| A D | dmub_dcn32.c | 37 #define REGS dmub->regs_dcn32 macro
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| A D | dmub_dcn401.c | 16 #define REGS dmub->regs_dcn401 macro
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| /drivers/gpu/drm/amd/amdgpu/ |
| A D | uvd_v3_1.c | 211 WREG32_FIELD(UVD_CGC_GATE, REGS, 0); in uvd_v3_1_set_dcm()
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| A D | uvd_v4_2.c | 640 WREG32_FIELD(UVD_CGC_GATE, REGS, 0); in uvd_v4_2_set_dcm()
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| /drivers/memory/tegra/ |
| A D | tegra210-emc-cc-r21021.c | 33 #define REGS (1 << 30) macro
|