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Searched refs:REG_BIT (Results 1 – 25 of 65) sorted by relevance

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/drivers/gpu/drm/xe/regs/
A Dxe_gt_regs.h50 #define MCR_MULTICAST REG_BIT(31)
65 #define LE_SCF_MASK REG_BIT(14)
71 #define LE_RSC_MASK REG_BIT(7)
73 #define LE_AOM_MASK REG_BIT(6)
86 #define CG_DIS_CNTLBUS REG_BIT(6)
94 #define AUX_INV REG_BIT(0)
202 #define L3CMPCTRL REG_BIT(23)
243 #define GRDOM_GUC REG_BIT(3)
244 #define GRDOM_FULL REG_BIT(0)
456 #define LMEM_EN REG_BIT(31)
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A Dxe_guc_regs.h21 #define DRB_VALID REG_BIT(0)
25 #define GTCR_INVALIDATE REG_BIT(0)
41 #define GS_MIA_IN_RESET REG_BIT(0)
55 #define GUC_MSGCH_ENABLE REG_BIT(4)
78 #define HUC_UKERNEL REG_BIT(9)
79 #define UOS_MOVE REG_BIT(4)
80 #define START_DMA REG_BIT(0)
102 #define HUC_FW_VERIFIED REG_BIT(7)
128 #define GUC_INTR_SEM_SIG REG_BIT(12)
131 #define GUC_INTR_DMA_DONE REG_BIT(9)
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A Dxe_irq_regs.h12 #define GU_MISC_GSE REG_BIT(27)
15 #define DG1_MSTR_IRQ REG_BIT(31)
19 #define MASTER_IRQ REG_BIT(31)
20 #define GU_MISC_IRQ REG_BIT(29)
21 #define DISPLAY_IRQ REG_BIT(16)
22 #define I2C_IRQ REG_BIT(12)
32 #define INTR_GSC REG_BIT(31)
33 #define INTR_GUC REG_BIT(25)
34 #define INTR_MGUC REG_BIT(24)
35 #define INTR_BCS8 REG_BIT(23)
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A Dxe_oa_regs.h10 #define GT_NOA_ENABLE REG_BIT(9)
25 #define OAR_OACONTROL_COUNTER_ENABLE REG_BIT(0)
29 #define OA_COUNTER_RESUME REG_BIT(0)
34 #define OAG_OAGLBCTXCTRL_TIMER_ENABLE REG_BIT(1)
35 #define OAG_OAGLBCTXCTRL_COUNTER_RESUME REG_BIT(0)
50 #define OAG_OACONTROL_OA_COUNTER_ENABLE REG_BIT(0)
70 #define OASTATUS_MMIO_TRG_Q_FULL REG_BIT(6)
71 #define OASTATUS_COUNTER_OVERFLOW REG_BIT(2)
72 #define OASTATUS_BUFFER_OVERFLOW REG_BIT(1)
73 #define OASTATUS_REPORT_LOST REG_BIT(0)
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A Dxe_engine_regs.h66 #define IDLE_MSG_DISABLE REG_BIT(0)
110 #define GHWSP_CSB_REPORT_DIS REG_BIT(15)
112 #define CS_PRIORITY_MEM_READ REG_BIT(7)
119 #define REPLAY_MODE_GRANULARITY REG_BIT(0)
127 #define BCS_SWCTRL_DISABLE_256B REG_BIT(2)
142 #define CTX_CTRL_PXP_ENABLE REG_BIT(10)
144 #define CTX_CTRL_RUN_ALONE REG_BIT(7)
158 #define STOP_RING REG_BIT(8)
186 #define EL_CTRL_LOAD REG_BIT(0)
208 #define ALNUNIT_CLKGATE_DIS REG_BIT(13)
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/drivers/gpu/drm/i915/display/
A Dintel_dsb_regs.h18 #define DSB_ENABLE REG_BIT(31)
19 #define DSB_BUF_REITERATE REG_BIT(29)
20 #define DSB_WAIT_FOR_VBLANK REG_BIT(28)
21 #define DSB_WAIT_FOR_LINE_IN REG_BIT(27)
22 #define DSB_HALT REG_BIT(16)
23 #define DSB_NON_POSTED REG_BIT(8)
24 #define DSB_STATUS_BUSY REG_BIT(0)
32 #define DSB_POLL_ENABLE REG_BIT(31)
41 #define DSB_DEWAKE_STATUS REG_BIT(30)
46 #define DSB_SAFE_WINDOW REG_BIT(19)
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A Dintel_psr_regs.h14 #define EXITLINE_ENABLE REG_BIT(31)
28 #define EDP_PSR_ENABLE REG_BIT(31)
29 #define BDW_PSR_SINGLE_FRAME REG_BIT(30)
31 #define EDP_PSR_LINK_STANDBY REG_BIT(27)
41 #define EDP_PSR_SKIP_AUX_EXIT REG_BIT(12)
42 #define EDP_PSR_TP_MASK REG_BIT(11)
75 #define TGL_PSR_ERROR REG_BIT(2)
76 #define TGL_PSR_POST_EXIT REG_BIT(1)
77 #define TGL_PSR_PRE_ENTRY REG_BIT(0)
158 #define EDP_PSR2_ENABLE REG_BIT(31)
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A Dintel_hdcp_regs.h15 #define HDCP_AKSV_SEND_TRIGGER REG_BIT(31)
17 #define HDCP_KEY_LOAD_TRIGGER REG_BIT(8)
19 #define HDCP_FUSE_IN_PROGRESS REG_BIT(7)
20 #define HDCP_FUSE_ERROR REG_BIT(6)
21 #define HDCP_FUSE_DONE REG_BIT(5)
22 #define HDCP_KEY_LOAD_STATUS REG_BIT(1)
23 #define HDCP_KEY_LOAD_DONE REG_BIT(0)
49 #define HDCP_SHA1_BUSY REG_BIT(16)
50 #define HDCP_SHA1_READY REG_BIT(17)
52 #define HDCP_SHA1_V_MATCH REG_BIT(19)
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A Dintel_fbc_regs.h12 #define FBC_CTL_EN REG_BIT(31)
13 #define FBC_CTL_PERIODIC REG_BIT(30)
16 #define FBC_CTL_STOP_ON_MOD REG_BIT(15)
24 #define FBC_CMD_COMPRESS REG_BIT(0)
27 #define FBC_STAT_COMPRESSED REG_BIT(30)
28 #define FBC_STAT_MODIFIED REG_BIT(29)
31 #define FBC_CTL_FENCE_DBL REG_BIT(4)
43 #define FBC_MOD_NUM_VALID REG_BIT(0)
57 #define DPFC_CTL_EN REG_BIT(31)
113 #define ILK_FBC_RT_VALID REG_BIT(0)
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A Dintel_display_regs.h114 #define IPS_ENABLE REG_BIT(31)
115 #define IPS_FALSE_COLOR REG_BIT(4)
319 #define DPCE_GATING_DIS REG_BIT(17)
635 #define DP_PORT_EN REG_BIT(31)
670 #define EDP_PLL_ENABLE REG_BIT(14)
678 #define DP_DETECTED REG_BIT(2)
1275 #define GEN8_PIPE_VSYNC REG_BIT(1)
1428 #define ILK_DESKTOP REG_BIT(23)
1994 #define TRANS_ENABLE REG_BIT(31)
2653 #define PLL_ENABLE REG_BIT(31)
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A Dintel_dvo_regs.h15 #define DVO_ENABLE REG_BIT(31)
16 #define DVO_PIPE_SEL_MASK REG_BIT(30)
22 #define DVO_INTERRUPT_SELECT REG_BIT(27)
25 #define DVO_USE_VGA_SYNC REG_BIT(15)
26 #define DVO_DATA_ORDER_MASK REG_BIT(14)
29 #define DVO_VSYNC_DISABLE REG_BIT(11)
30 #define DVO_HSYNC_DISABLE REG_BIT(10)
31 #define DVO_VSYNC_TRISTATE REG_BIT(9)
32 #define DVO_HSYNC_TRISTATE REG_BIT(8)
33 #define DVO_BORDER_ENABLE REG_BIT(7)
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A Dintel_cx0_phy_regs.h106 #define XELPDP_PORT_REVERSAL REG_BIT(16)
125 #define XELPDP_LANE_PIPE_RESET(lane) _PICK(lane, REG_BIT(31), REG_BIT(30))
126 #define XELPDP_LANE_PHY_CURRENT_STATUS(lane) _PICK(lane, REG_BIT(29), REG_BIT(28))
127 #define XELPDP_LANE_POWERDOWN_UPDATE(lane) _PICK(lane, REG_BIT(25), REG_BIT(24))
264 #define C10_TX0_TX_MPLLB_SEL REG_BIT(4)
339 #define C20_PHY_TX_DCC_BYPASS REG_BIT(12)
351 #define C20_MPLLA_FRACEN REG_BIT(14)
352 #define C20_FB_CLK_DIV4_EN REG_BIT(13)
361 #define C20_MPLLB_FRACEN REG_BIT(13)
364 #define C20_PHY_USE_MPLLB REG_BIT(7)
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A Dintel_vga_regs.h14 #define VGA_DISP_DISABLE REG_BIT(31)
15 #define VGA_2X_MODE REG_BIT(30) /* pre-ilk */
16 #define VGA_PIPE_SEL_MASK REG_BIT(29) /* pre-ivb */
20 #define VGA_BORDER_ENABLE REG_BIT(26)
21 #define VGA_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
23 #define VGA_PALETTE_READ_SEL REG_BIT(23) /* pre-ivb */
26 #define VGA_LEGACY_8BIT_PALETTE_ENABLE REG_BIT(20)
27 #define VGA_PALETTE_BYPASS REG_BIT(19)
28 #define VGA_NINE_DOT_DISABLE REG_BIT(18)
29 #define VGA_PALETTE_READ_SEL_HI_CHV REG_BIT(15) /* chv */
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A Dintel_dp_aux_regs.h46 #define DP_AUX_CH_CTL_SEND_BUSY REG_BIT(31)
47 #define DP_AUX_CH_CTL_DONE REG_BIT(30)
48 #define DP_AUX_CH_CTL_INTERRUPT REG_BIT(29)
49 #define DP_AUX_CH_CTL_TIME_OUT_ERROR REG_BIT(28)
55 #define DP_AUX_CH_CTL_RECEIVE_ERROR REG_BIT(25)
62 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT REG_BIT(15)
65 #define DP_AUX_CH_CTL_SYNC_TEST REG_BIT(13) /* pre-hsw */
67 #define DP_AUX_CH_CTL_DEGLITCH_TEST REG_BIT(12) /* pre-hsw */
70 #define DP_AUX_CH_CTL_TBT_IO REG_BIT(11) /* icl+ */
103 #define XE2LPD_PICA_CTL_POWER_REQUEST REG_BIT(31)
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A Dvlv_dpio_phy_regs.h41 #define DPIO_ENABLE_CALIBRATION REG_BIT(11)
48 #define DPIO_REFSEL_OVERRIDE REG_BIT(27)
76 #define DPIO_PCS_TX_LANE1_RESET REG_BIT(7)
178 #define DPIO_TX_OCALINIT_EN REG_BIT(31)
204 #define DPIO_CHV_SECOND_MOD REG_BIT(8)
251 #define DPIO_PLL_FREQLOCK REG_BIT(1)
252 #define DPIO_PLL_LOCK REG_BIT(0)
257 #define DPIO_AFC_RECAL REG_BIT(14)
258 #define DPIO_DCLKP_EN REG_BIT(13)
288 #define DPIO_LRC_BYPASS REG_BIT(3)
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A Dintel_crt_regs.h14 #define ADPA_DAC_ENABLE REG_BIT(31)
15 #define ADPA_PIPE_SEL_MASK REG_BIT(30)
23 #define ADPA_CRT_HOTPLUG_ENABLE REG_BIT(23)
24 #define ADPA_CRT_HOTPLUG_PERIOD_MASK REG_BIT(22)
27 #define ADPA_CRT_HOTPLUG_WARMUP_MASK REG_BIT(21)
30 #define ADPA_CRT_HOTPLUG_SAMPLE_MASK REG_BIT(20)
42 #define ADPA_USE_VGA_HVPOLARITY REG_BIT(15)
43 #define ADPA_HSYNC_CNTL_DISABLE REG_BIT(11)
44 #define ADPA_VSYNC_CNTL_DISABLE REG_BIT(10)
45 #define ADPA_VSYNC_ACTIVE_HIGH REG_BIT(4)
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A Dbxt_dpio_phy_regs.h37 #define PORT_PLL_ENABLE REG_BIT(31)
38 #define PORT_PLL_LOCK REG_BIT(30)
39 #define PORT_PLL_REF_SEL REG_BIT(27)
41 #define PORT_PLL_POWER_STATE REG_BIT(25)
104 #define PHY_POWER_GOOD REG_BIT(16)
105 #define PHY_RESERVED REG_BIT(7)
143 #define GRC_DONE REG_BIT(22)
160 #define GRC_DIS REG_BIT(15)
161 #define GRC_RDY_OVRD REG_BIT(1)
262 #define DCC_DELAY_RANGE_1 REG_BIT(9)
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A Dintel_vrr_regs.h16 #define VRR_CTL_VRR_ENABLE REG_BIT(31)
17 #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
18 #define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
19 #define VRR_CTL_CMRR_ENABLE REG_BIT(27)
46 #define VRR_VMAXSHIFT_DEC REG_BIT(16)
54 #define VRR_STATUS_VMAX_REACHED REG_BIT(31)
56 #define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
57 #define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
58 #define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
98 #define TRANS_PUSH_EN REG_BIT(31)
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A Dintel_sprite_regs.h13 #define DVS_ENABLE REG_BIT(31)
14 #define DVS_PIPE_GAMMA_ENABLE REG_BIT(30)
21 #define DVS_PIPE_CSC_ENABLE REG_BIT(24)
22 #define DVS_SOURCE_KEY REG_BIT(22)
23 #define DVS_RGB_ORDER_XBGR REG_BIT(20)
30 #define DVS_ROTATE_180 REG_BIT(15)
32 #define DVS_TILED REG_BIT(10)
33 #define DVS_DEST_KEY REG_BIT(2)
142 #define SPRITE_TILED REG_BIT(10)
238 #define SP_ENABLE REG_BIT(31)
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A Dintel_dmc_regs.h285 #define PIPEDMC_ENABLE REG_BIT(0)
297 #define PIPEDMC_HALT REG_BIT(31)
298 #define PIPEDMC_STEP REG_BIT(27)
451 #define PIPEDMC_ERROR REG_BIT(2)
452 #define PIPEDMC_GTT_FAULT REG_BIT(1)
556 #define LNL_FQ_INTERRUPT REG_BIT(31)
559 #define LNL_FQ_EXECUTED REG_BIT(28)
571 #define PTL_FQ_INTERRUPT REG_BIT(31)
572 #define PTL_FQ_NEED_PUSH REG_BIT(30)
573 #define PTL_FQ_BLOCK_PUSH REG_BIT(29)
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/drivers/gpu/drm/i915/
A Di915_reg.h120 #define DEPRESENT REG_BIT(9)
123 #define LMEM_INIT REG_BIT(7)
124 #define DRIVERFLR REG_BIT(31)
282 #define HECI_H_CSR_IE REG_BIT(0)
283 #define HECI_H_CSR_IS REG_BIT(1)
284 #define HECI_H_CSR_IG REG_BIT(2)
285 #define HECI_H_CSR_RDY REG_BIT(3)
286 #define HECI_H_CSR_RST REG_BIT(4)
747 #define RATL_MASK REG_BIT(5)
1223 #define SGGI_DIS REG_BIT(15)
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/drivers/gpu/drm/i915/gt/
A Dintel_gt_regs.h331 #define RING_FAULT_VALID REG_BIT(0)
356 #define AUX_INV REG_BIT(0)
391 #define FAULT_GTT_SEL REG_BIT(4)
426 #define TBIMR_FAST_CLIP REG_BIT(5)
482 #define FD_END_COLLECT REG_BIT(5)
551 #define EN_32B_ACCESS REG_BIT(30)
699 #define GEN11_GRDOM_GUC REG_BIT(3)
906 #define IDLE_MSG_DISABLE REG_BIT(0)
1118 #define DISABLE_ECC REG_BIT(5)
1440 #define BCS_SRC_Y REG_BIT(0)
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A Dintel_engine_regs.h51 #define GEN6_BSD_GO_INDICATOR REG_BIT(4)
75 #define MI_FLUSH_ENABLE REG_BIT(12)
76 #define TGL_NESTED_BB_EN REG_BIT(12)
77 #define MODE_IDLE REG_BIT(9)
78 #define STOP_RING REG_BIT(8)
79 #define VS_TIMER_DISPATCH REG_BIT(6)
104 #define RESET_CTL_CAT_ERROR REG_BIT(2)
131 #define ECO_GATING_CX_ONLY REG_BIT(3)
133 #define ECO_FLIP_DONE REG_BIT(0)
235 #define EL_CTRL_LOAD REG_BIT(0)
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/drivers/gpu/drm/xe/instructions/
A Dxe_mi_commands.h29 #define MI_ARB_ENABLE REG_BIT(0)
38 #define MI_SDI_GGTT REG_BIT(22)
42 REG_BIT(21))
45 #define MI_LRI_LRM_CS_MMIO REG_BIT(19)
48 #define MI_LRI_FORCE_POSTED REG_BIT(12)
52 #define MI_SRM_USE_GGTT REG_BIT(22)
58 #define MI_INVALIDATE_TLB REG_BIT(18)
59 #define MI_FLUSH_DW_CCS REG_BIT(16)
64 #define MI_FLUSH_DW_USE_GTT REG_BIT(2)
67 #define MI_LRM_USE_GGTT REG_BIT(22)
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/drivers/gpu/drm/xe/tests/
A Dxe_rtp_test.c65 .expected_set_bits = REG_BIT(0) | REG_BIT(1),
66 .expected_clr_bits = REG_BIT(0) | REG_BIT(1),
85 .expected_set_bits = REG_BIT(0),
86 .expected_clr_bits = REG_BIT(0),
105 .expected_set_bits = REG_BIT(0) | REG_BIT(1) | REG_BIT(2),
106 .expected_clr_bits = REG_BIT(0) | REG_BIT(1) | REG_BIT(2),
159 .expected_set_bits = REG_BIT(0),
160 .expected_clr_bits = REG_BIT(0),
179 .expected_set_bits = REG_BIT(0),
180 .expected_clr_bits = REG_BIT(0),
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