Searched refs:REG_CLR (Results 1 – 8 of 8) sorted by relevance
| /drivers/thermal/ |
| A D | imx_thermal.c | 21 #define REG_CLR 0x8 macro
228 regmap_write(map, soc_data->panic_alarm_ctrl + REG_CLR, in imx_set_panic_temp()
248 regmap_write(map, soc_data->high_alarm_ctrl + REG_CLR, in imx_set_alarm_temp()
615 regmap_write(map, IMX6_MISC1 + REG_CLR, in imx_thermal_probe()
646 regmap_write(map, data->socdata->sensor_ctrl + REG_CLR, in imx_thermal_probe()
648 regmap_write(map, data->socdata->sensor_ctrl + REG_CLR, in imx_thermal_probe()
650 regmap_write(map, data->socdata->measure_freq_ctrl + REG_CLR, in imx_thermal_probe()
702 regmap_write(map, data->socdata->measure_freq_ctrl + REG_CLR, in imx_thermal_probe()
712 regmap_write(map, data->socdata->sensor_ctrl + REG_CLR, in imx_thermal_probe()
806 ret = regmap_write(map, socdata->sensor_ctrl + REG_CLR, in imx_thermal_runtime_suspend()
[all …]
|
| /drivers/gpu/drm/mxsfb/ |
| A D | mxsfb_kms.c | 215 writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_CLR); in mxsfb_disable_controller()
238 writel(mask, addr + REG_CLR); in clear_poll_bit()
256 writel(CTRL_CLKGATE, mxsfb->base + LCDC_CTRL + REG_CLR); in mxsfb_reset_block()
269 writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_reset_block()
428 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_crtc_enable_vblank()
439 writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_crtc_disable_vblank()
440 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_crtc_disable_vblank()
|
| A D | mxsfb_drv.c | 173 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_irq_handler()
185 writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_irq_disable()
186 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_irq_disable()
|
| A D | mxsfb_regs.h | 13 #define REG_CLR 8 macro
|
| A D | lcdif_regs.h | 12 #define REG_CLR 8 macro
|
| A D | lcdif_kms.c | 397 writel(CTRL_SW_RESET, lcdif->base + LCDC_V8_CTRL + REG_CLR); in lcdif_reset_block()
|
| /drivers/phy/freescale/ |
| A D | phy-fsl-imx8qm-lvds-phy.c | 19 #define REG_CLR 0x8 macro
154 regmap_write(priv->regmap, PHY_CTRL + REG_CLR, in mixel_lvds_phy_power_off()
157 regmap_write(priv->regmap, PHY_CTRL + REG_CLR, in mixel_lvds_phy_power_off()
|
| /drivers/misc/rp1/ |
| A D | rp1_pci.c | 22 #define REG_CLR 0xc00 macro
57 iowrite32(value, rp1->bar1 + RP1_PCIE_APBS_BASE + REG_CLR + MSIX_CFG(hwirq)); in msix_cfg_clr()
|
Completed in 24 milliseconds