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Searched refs:REG_FIELD_GET (Results 1 – 25 of 83) sorted by relevance

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/drivers/gpu/drm/xe/
A Dxe_device_sysfs.c90 if (REG_FIELD_GET(V1_FAN_PROVISIONED, cap)) { in lb_fan_control_version_show()
101 major = REG_FIELD_GET(MAJOR_VERSION_MASK, ver_low); in lb_fan_control_version_show()
102 minor = REG_FIELD_GET(MINOR_VERSION_MASK, ver_low); in lb_fan_control_version_show()
129 if (REG_FIELD_GET(VR_PARAMS_PROVISIONED, cap)) { in lb_voltage_regulator_version_show()
140 major = REG_FIELD_GET(MAJOR_VERSION_MASK, ver_low); in lb_voltage_regulator_version_show()
141 minor = REG_FIELD_GET(MINOR_VERSION_MASK, ver_low); in lb_voltage_regulator_version_show()
171 if (REG_FIELD_GET(V1_FAN_SUPPORTED, cap)) { in late_bind_create_files()
177 if (REG_FIELD_GET(VR_PARAMS_SUPPORTED, cap)) in late_bind_create_files()
199 if (REG_FIELD_GET(V1_FAN_SUPPORTED, cap)) in late_bind_remove_files()
202 if (REG_FIELD_GET(VR_PARAMS_SUPPORTED, cap)) in late_bind_remove_files()
[all …]
A Dxe_mocs.c286 REG_FIELD_GET(L3_SCC_MASK, reg_val), in xelp_lncf_dump()
287 REG_FIELD_GET(L3_CACHEABILITY_MASK, reg_val), in xelp_lncf_dump()
318 REG_FIELD_GET(LE_TGT_CACHE_MASK, reg_val), in xelp_mocs_dump()
319 REG_FIELD_GET(LE_LRUM_MASK, reg_val), in xelp_mocs_dump()
322 REG_FIELD_GET(LE_SCC_MASK, reg_val), in xelp_mocs_dump()
323 REG_FIELD_GET(LE_PFM_MASK, reg_val), in xelp_mocs_dump()
325 REG_FIELD_GET(LE_COS_MASK, reg_val), in xelp_mocs_dump()
326 REG_FIELD_GET(LE_SSE_MASK, reg_val), in xelp_mocs_dump()
392 REG_FIELD_GET(L3_CACHEABILITY_MASK, reg_val), in xehp_lncf_dump()
435 REG_FIELD_GET(L3_CACHEABILITY_MASK, reg_val), in pvc_mocs_dump()
[all …]
A Dxe_gt_topology.c146 u32 meml3_en = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, fuse3); in load_l3_bank_mask()
148 u32 bank_val = REG_FIELD_GET(XE3_L3BANK_ENABLE, mirror_l3bank_enable); in load_l3_bank_mask()
155 u32 meml3_en = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, fuse3); in load_l3_bank_mask()
156 u32 bank_val = REG_FIELD_GET(XE2_GT_L3_MODE_MASK, fuse3); in load_l3_bank_mask()
164 u32 meml3_en = REG_FIELD_GET(MEML3_EN_MASK, fuse3); in load_l3_bank_mask()
166 u32 bank_val = REG_FIELD_GET(GT_L3_EXC_MASK, fuse4); in load_l3_bank_mask()
175 u32 meml3_en = REG_FIELD_GET(MEML3_EN_MASK, fuse3); in load_l3_bank_mask()
176 u32 bank_val = REG_FIELD_GET(XEHPC_GT_L3_MODE_MASK, fuse3); in load_l3_bank_mask()
185 u32 mask = REG_FIELD_GET(MEML3_EN_MASK, fuse3); in load_l3_bank_mask()
191 u32 mask = REG_FIELD_GET(XELP_GT_L3_MODE_MASK, ~fuse3); in load_l3_bank_mask()
A Dxe_pat.c241 mem_type = REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat); in xehp_dump()
271 REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat), in xehpc_dump()
304 REG_FIELD_GET(XELPG_L4_POLICY_MASK, pat), in xelpg_dump()
343 REG_FIELD_GET(XE2_L3_CLOS, pat), in xe2_dump()
344 REG_FIELD_GET(XE2_L3_POLICY, pat), in xe2_dump()
345 REG_FIELD_GET(XE2_L4_POLICY, pat), in xe2_dump()
346 REG_FIELD_GET(XE2_COH_MODE, pat), in xe2_dump()
363 REG_FIELD_GET(XE2_L3_CLOS, pat), in xe2_dump()
364 REG_FIELD_GET(XE2_L3_POLICY, pat), in xe2_dump()
365 REG_FIELD_GET(XE2_L4_POLICY, pat), in xe2_dump()
[all …]
A Dxe_guc_pc.c388 pc->rpa_freq = decode_freq(REG_FIELD_GET(MTL_RPA_MASK, reg)); in mtl_update_rpa_value()
401 pc->rpe_freq = decode_freq(REG_FIELD_GET(MTL_RPE_MASK, reg)); in mtl_update_rpe_value()
417 pc->rpa_freq = REG_FIELD_GET(RP0_MASK, reg) * GT_FREQUENCY_MULTIPLIER; in tgl_update_rpa_value()
420 pc->rpa_freq = REG_FIELD_GET(RPA_MASK, reg) * GT_FREQUENCY_MULTIPLIER; in tgl_update_rpa_value()
480 freq = REG_FIELD_GET(MTL_CAGF_MASK, freq); in xe_guc_pc_get_act_freq()
483 freq = REG_FIELD_GET(CAGF_MASK, freq); in xe_guc_pc_get_act_freq()
496 freq = REG_FIELD_GET(REQ_RATIO_MASK, freq); in get_cur_freq()
746 gt_c_state = REG_FIELD_GET(MTL_CC_MASK, reg); in xe_guc_pc_c_status()
749 gt_c_state = REG_FIELD_GET(RCN_MASK, reg); in xe_guc_pc_c_status()
802 pc->rp0_freq = decode_freq(REG_FIELD_GET(MTL_RP0_CAP_MASK, reg)); in mtl_init_fused_rp_values()
[all …]
A Dxe_vram.c176 nodes = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, reg); in get_flat_ccs_offset()
180 offset_lo = REG_FIELD_GET(XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK, reg); in get_flat_ccs_offset()
183 offset_hi = REG_FIELD_GET(XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK, reg); in get_flat_ccs_offset()
196 offset = (u64)REG_FIELD_GET(XEHP_FLAT_CCS_PTR, reg) * SZ_64K; in get_flat_ccs_offset()
256 *tile_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg) * SZ_1G; in tile_vram_size()
257 *tile_offset = (u64)REG_FIELD_GET(GENMASK(7, 1), reg) * SZ_1G; in tile_vram_size()
A Dxe_hwmon.c312 reg_val = REG_FIELD_GET(PWR_LIM_VAL, reg_val); in xe_hwmon_power_max_read()
318 min = REG_FIELD_GET(PKG_MIN_PWR, reg_val); in xe_hwmon_power_max_read()
319 max = REG_FIELD_GET(PKG_MAX_PWR, reg_val); in xe_hwmon_power_max_read()
424 reg_val = REG_FIELD_GET(PKG_TDP, reg_val); in xe_hwmon_power_rated_max_read()
523 x = REG_FIELD_GET(PWR_LIM_TIME_X, r); in xe_hwmon_power_max_interval_show()
524 y = REG_FIELD_GET(PWR_LIM_TIME_Y, r); in xe_hwmon_power_max_interval_show()
577 x = REG_FIELD_GET(PKG_MAX_WIN_X, r); in xe_hwmon_power_max_interval_store()
578 y = REG_FIELD_GET(PKG_MAX_WIN_Y, r); in xe_hwmon_power_max_interval_store()
814 *val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE; in xe_hwmon_temp_read()
1278 hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit); in xe_hwmon_get_preregistration_info()
[all …]
A Dxe_survivability_mode.c63 return REG_FIELD_GET(AUXINFO_HISTORY_OFFSET, reg_value); in aux_history_offset()
92 id = REG_FIELD_GET(OVERFLOW_REG_OFFSET, reg_value); in populate_survivability_info()
98 id = REG_FIELD_GET(AUXINFO_REG_OFFSET, reg_value); in populate_survivability_info()
242 survivability->boot_status = REG_FIELD_GET(BOOT_STATUS, data); in xe_survivability_mode_is_requested()
A Dxe_gt_mcr.c256 u32 mslice_mask = REG_FIELD_GET(MEML3_EN_MASK, in init_steering_l3bank()
258 u32 bank_mask = REG_FIELD_GET(GT_L3_EXC_MASK, in init_steering_l3bank()
269 u32 mslice_mask = REG_FIELD_GET(MEML3_EN_MASK, in init_steering_l3bank()
281 u32 fuse = REG_FIELD_GET(L3BANK_MASK, in init_steering_l3bank()
291 u32 mask = REG_FIELD_GET(MEML3_EN_MASK, in init_steering_mslice()
415 u32 mask = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, in init_steering_sqidi_psmi()
A Dxe_gt_clock.c30 u32 crystal_clock = REG_FIELD_GET(RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, in read_crystal_clock()
90 freq >>= 3 - REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, c0); in xe_gt_clock_init()
A Dxe_guc.c984 u32 uk_val = REG_FIELD_GET(GS_UKERNEL_MASK, status); in guc_load_done()
985 u32 br_val = REG_FIELD_GET(GS_BOOTROM_MASK, status); in guc_load_done()
1106 REG_FIELD_GET(GS_BOOTROM_MASK, status), in guc_wait_ucode()
1107 REG_FIELD_GET(GS_UKERNEL_MASK, status)); in guc_wait_ucode()
1111 u32 ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, status); in guc_wait_ucode()
1118 REG_FIELD_GET(GS_MIA_IN_RESET, status), in guc_wait_ucode()
1120 REG_FIELD_GET(GS_MIA_MASK, status), in guc_wait_ucode()
1121 REG_FIELD_GET(GS_AUTH_STATUS_MASK, status)); in guc_wait_ucode()
1636 REG_FIELD_GET(GS_BOOTROM_MASK, status)); in xe_guc_print_info()
1638 REG_FIELD_GET(GS_UKERNEL_MASK, status)); in xe_guc_print_info()
[all …]
/drivers/gpu/drm/i915/gt/uc/
A Dintel_guc_fw.c100 u32 uk_val = REG_FIELD_GET(GS_UKERNEL_MASK, val); in guc_load_done()
101 u32 br_val = REG_FIELD_GET(GS_BOOTROM_MASK, val); in guc_load_done()
197 REG_FIELD_GET(GS_BOOTROM_MASK, status), in guc_wait_ucode()
198 REG_FIELD_GET(GS_UKERNEL_MASK, status)); in guc_wait_ucode()
204 u32 ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, status); in guc_wait_ucode()
205 u32 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, status); in guc_wait_ucode()
210 REG_FIELD_GET(GS_MIA_IN_RESET, status), in guc_wait_ucode()
212 REG_FIELD_GET(GS_MIA_MASK, status), in guc_wait_ucode()
213 REG_FIELD_GET(GS_AUTH_STATUS_MASK, status)); in guc_wait_ucode()
/drivers/gpu/drm/i915/display/
A Dintel_vdsc.c887 vdsc_cfg->bits_per_component = REG_FIELD_GET(DSC_PPS0_BPC_MASK, pps_temp); in intel_dsc_get_pps_config()
888 vdsc_cfg->line_buf_depth = REG_FIELD_GET(DSC_PPS0_LINE_BUF_DEPTH_MASK, pps_temp); in intel_dsc_get_pps_config()
899 vdsc_cfg->bits_per_pixel = REG_FIELD_GET(DSC_PPS1_BPP_MASK, pps_temp); in intel_dsc_get_pps_config()
910 vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PPS2_PIC_HEIGHT_MASK, pps_temp); in intel_dsc_get_pps_config()
915 vdsc_cfg->slice_width = REG_FIELD_GET(DSC_PPS3_SLICE_WIDTH_MASK, pps_temp); in intel_dsc_get_pps_config()
916 vdsc_cfg->slice_height = REG_FIELD_GET(DSC_PPS3_SLICE_HEIGHT_MASK, pps_temp); in intel_dsc_get_pps_config()
935 vdsc_cfg->flatness_min_qp = REG_FIELD_GET(DSC_PPS6_FLATNESS_MIN_QP_MASK, pps_temp); in intel_dsc_get_pps_config()
941 vdsc_cfg->nfl_bpg_offset = REG_FIELD_GET(DSC_PPS7_NFL_BPG_OFFSET_MASK, pps_temp); in intel_dsc_get_pps_config()
947 vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_PPS8_INITIAL_OFFSET_MASK, pps_temp); in intel_dsc_get_pps_config()
948 vdsc_cfg->final_offset = REG_FIELD_GET(DSC_PPS8_FINAL_OFFSET_MASK, pps_temp); in intel_dsc_get_pps_config()
[all …]
A Dintel_pmdemand.c422 REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
424 REG_FIELD_GET(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
426 REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
428 REG_FIELD_GET(XELPDP_PMDEMAND_PHYS_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
431 REG_FIELD_GET(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, reg2); in intel_pmdemand_init_pmdemand_params()
433 REG_FIELD_GET(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, reg2); in intel_pmdemand_init_pmdemand_params()
437 REG_FIELD_GET(XE3_PMDEMAND_PIPES_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
440 REG_FIELD_GET(XELPDP_PMDEMAND_PIPES_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
442 REG_FIELD_GET(XELPDP_PMDEMAND_DBUFS_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
445 REG_FIELD_GET(XELPDP_PMDEMAND_SCALERS_MASK, reg2); in intel_pmdemand_init_pmdemand_params()
[all …]
A Dintel_lvds.c95 *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK_CPT, val); in intel_lvds_port_enabled()
97 *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK, val); in intel_lvds_port_enabled()
165 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); in intel_lvds_pps_get_hw_state()
166 pps->delays.power_up = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
167 pps->delays.backlight_on = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
170 pps->delays.power_down = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
171 pps->delays.backlight_off = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
174 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); in intel_lvds_pps_get_hw_state()
175 val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
A Dintel_color.c877 u16 red = REG_FIELD_GET(PALETTE_10BIT_RED_LDW_MASK, ldw) | in i9xx_lut_10_pack()
878 REG_FIELD_GET(PALETTE_10BIT_RED_UDW_MASK, udw) << 8; in i9xx_lut_10_pack()
880 REG_FIELD_GET(PALETTE_10BIT_GREEN_UDW_MASK, udw) << 8; in i9xx_lut_10_pack()
882 REG_FIELD_GET(PALETTE_10BIT_BLUE_UDW_MASK, udw) << 8; in i9xx_lut_10_pack()
924 entry->red = REG_FIELD_GET(PALETTE_RED_MASK, udw) << 8 | in i965_lut_10p6_pack()
925 REG_FIELD_GET(PALETTE_RED_MASK, ldw); in i965_lut_10p6_pack()
927 REG_FIELD_GET(PALETTE_GREEN_MASK, ldw); in i965_lut_10p6_pack()
929 REG_FIELD_GET(PALETTE_BLUE_MASK, ldw); in i965_lut_10p6_pack()
971 REG_FIELD_GET(PREC_PALETTE_12P4_RED_LDW_MASK, ldw); in ilk_lut_12p4_pack()
973 REG_FIELD_GET(PREC_PALETTE_12P4_GREEN_LDW_MASK, ldw); in ilk_lut_12p4_pack()
[all …]
A Dintel_flipq.c247 REG_FIELD_GET(PIPEDMC_FPQ_PLANEQ_3_TP_MASK, tmp), in intel_flipq_dump()
248 REG_FIELD_GET(PIPEDMC_FPQ_PLANEQ_2_TP_MASK, tmp), in intel_flipq_dump()
249 REG_FIELD_GET(PIPEDMC_FPQ_PLANEQ_1_TP_MASK, tmp), in intel_flipq_dump()
250 REG_FIELD_GET(PIPEDMC_FPQ_GENERALQ_TP_MASK, tmp), in intel_flipq_dump()
251 REG_FIELD_GET(PIPEDMC_FPQ_FASTQ_TP_MASK, tmp)); in intel_flipq_dump()
A Dintel_vga.c58 pipe = REG_FIELD_GET(VGA_PIPE_SEL_MASK_CHV, tmp); in intel_vga_disable()
60 pipe = REG_FIELD_GET(VGA_PIPE_SEL_MASK, tmp); in intel_vga_disable()
A Dintel_pfit.c620 pipe = REG_FIELD_GET(PF_PIPE_SEL_MASK_IVB, ctl); in ilk_pfit_get_config()
630 REG_FIELD_GET(PF_WIN_XPOS_MASK, pos), in ilk_pfit_get_config()
631 REG_FIELD_GET(PF_WIN_YPOS_MASK, pos), in ilk_pfit_get_config()
632 REG_FIELD_GET(PF_WIN_XSIZE_MASK, size), in ilk_pfit_get_config()
633 REG_FIELD_GET(PF_WIN_YSIZE_MASK, size)); in ilk_pfit_get_config()
710 pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp); in i9xx_pfit_get_config()
A Dintel_crt.c99 *pipe = REG_FIELD_GET(ADPA_PIPE_SEL_MASK_CPT, val); in intel_crt_port_enabled()
101 *pipe = REG_FIELD_GET(ADPA_PIPE_SEL_MASK, val); in intel_crt_port_enabled()
716 vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1; in intel_crt_load_detect()
717 vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1; in intel_crt_load_detect()
719 vblank_start = REG_FIELD_GET(VBLANK_START_MASK, vblank) + 1; in intel_crt_load_detect()
720 vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1; in intel_crt_load_detect()
756 u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1; in intel_crt_load_detect()
A Dintel_bw.c90 dclk_ratio = REG_FIELD_GET(DG1_QCLK_RATIO_MASK, val); in dg1_mchbar_read_qgv_point_info()
105 sp->t_rp = REG_FIELD_GET(DG1_DRAM_T_RP_MASK, val); in dg1_mchbar_read_qgv_point_info()
106 sp->t_rdpre = REG_FIELD_GET(DG1_DRAM_T_RDPRE_MASK, val); in dg1_mchbar_read_qgv_point_info()
109 sp->t_rcd = REG_FIELD_GET(DG1_DRAM_T_RCD_MASK, val); in dg1_mchbar_read_qgv_point_info()
110 sp->t_ras = REG_FIELD_GET(DG1_DRAM_T_RAS_MASK, val); in dg1_mchbar_read_qgv_point_info()
230 dclk = REG_FIELD_GET(MTL_DCLK_MASK, val); in mtl_read_qgv_point_info()
232 sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val); in mtl_read_qgv_point_info()
233 sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val); in mtl_read_qgv_point_info()
235 sp->t_rdpre = REG_FIELD_GET(MTL_TRDPRE_MASK, val2); in mtl_read_qgv_point_info()
236 sp->t_ras = REG_FIELD_GET(MTL_TRAS_MASK, val2); in mtl_read_qgv_point_info()
/drivers/gpu/drm/i915/gt/
A Dintel_sseu.c239 eu_en_fuse = REG_FIELD_GET(XEHP_EU_ENA_MASK, in xehp_sseu_info_init()
273 s_en = REG_FIELD_GET(GEN11_GT_S_ENA_MASK, in gen12_sseu_info_init()
280 eu_en_fuse = ~REG_FIELD_GET(GEN11_EU_DIS_MASK, in gen12_sseu_info_init()
310 s_en = REG_FIELD_GET(GEN11_GT_S_ENA_MASK, in gen11_sseu_info_init()
316 eu_en = ~REG_FIELD_GET(GEN11_EU_DIS_MASK, in gen11_sseu_info_init()
339 REG_FIELD_GET(CHV_FGT_EU_DIS_SS0_R0_MASK, fuse) | in cherryview_sseu_info_init()
348 REG_FIELD_GET(CHV_FGT_EU_DIS_SS1_R0_MASK, fuse) | in cherryview_sseu_info_init()
502 REG_FIELD_GET(GEN8_EU_DIS0_S0_MASK, eu_disable0); in bdw_sseu_info_init()
504 REG_FIELD_GET(GEN8_EU_DIS0_S1_MASK, eu_disable0) | in bdw_sseu_info_init()
507 REG_FIELD_GET(GEN8_EU_DIS1_S2_MASK, eu_disable1) | in bdw_sseu_info_init()
[all …]
A Dintel_gt_clock_utils.c81 freq >>= 3 - REG_FIELD_GET(GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, c0); in gen11_read_clock_frequency()
102 freq >>= 3 - REG_FIELD_GET(CTC_SHIFT_PARAMETER_MASK, ctc_reg); in gen9_read_clock_frequency()
/drivers/gpu/drm/i915/
A Di915_hwmon.c110 reg_value = REG_FIELD_GET(field_msk, reg_value); in hwm_field_read_and_scale()
180 x = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_X, r); in hwm_power1_max_interval_show()
181 y = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_Y, r); in hwm_power1_max_interval_show()
224 x = REG_FIELD_GET(PKG_MAX_WIN_X, r); in hwm_power1_max_interval_store()
225 y = REG_FIELD_GET(PKG_MAX_WIN_Y, r); in hwm_power1_max_interval_store()
340 *val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE; in hwm_temp_read()
430 min = REG_FIELD_GET(PKG_MIN_PWR, r); in hwm_power_max_read()
432 max = REG_FIELD_GET(PKG_MAX_PWR, r); in hwm_power_max_read()
520 *val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval), in hwm_power_read()
888 hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit); in hwm_get_preregistration_info()
[all …]
/drivers/gpu/drm/xe/regs/
A Dxe_irq_regs.h54 #define INTR_ENGINE_INSTANCE(x) REG_FIELD_GET(GENMASK(25, 20), x)
55 #define INTR_ENGINE_CLASS(x) REG_FIELD_GET(GENMASK(18, 16), x)
56 #define INTR_ENGINE_INTR(x) REG_FIELD_GET(GENMASK(15, 0), x)

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