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Searched refs:REG_GENMASK (Results 1 – 25 of 70) sorted by relevance

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/drivers/gpu/drm/i915/display/
A Dintel_snps_phy_regs.h23 #define SNPS_PHY_MPLLB_CP_INT REG_GENMASK(31, 25)
24 #define SNPS_PHY_MPLLB_CP_INT_GS REG_GENMASK(23, 17)
25 #define SNPS_PHY_MPLLB_CP_PROP REG_GENMASK(15, 9)
26 #define SNPS_PHY_MPLLB_CP_PROP_GS REG_GENMASK(7, 1)
32 #define SNPS_PHY_MPLLB_V2I REG_GENMASK(27, 26)
33 #define SNPS_PHY_MPLLB_FREQ_VCO REG_GENMASK(25, 24)
38 #define SNPS_PHY_MPLLB_TX_CLK_DIV REG_GENMASK(7, 5)
44 #define SNPS_PHY_MPLLB_FRACN_DEN REG_GENMASK(15, 0)
71 #define SNPS_PHY_TX_EQ_MAIN REG_GENMASK(23, 18)
72 #define SNPS_PHY_TX_EQ_POST REG_GENMASK(15, 10)
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A Dvlv_dpio_phy_regs.h27 #define DPIO_S1_DIV_MASK REG_GENMASK(30, 28)
33 #define DPIO_K_DIV_MASK REG_GENMASK(27, 24)
35 #define DPIO_P1_DIV_MASK REG_GENMASK(23, 21)
37 #define DPIO_P2_DIV_MASK REG_GENMASK(20, 16)
39 #define DPIO_N_DIV_MASK REG_GENMASK(15, 12)
42 #define DPIO_M1_DIV_MASK REG_GENMASK(10, 8)
44 #define DPIO_M2_DIV_MASK REG_GENMASK(7, 0)
49 #define DPIO_PLL_MODESEL_MASK REG_GENMASK(26, 24)
188 #define DPIO_CHV_M2_DIV_MASK REG_GENMASK(7, 0)
192 #define DPIO_CHV_N_DIV_MASK REG_GENMASK(11, 8)
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A Dintel_psr_regs.h15 #define EXITLINE_MASK REG_GENMASK(12, 0)
37 #define EDP_PSR_MAX_SLEEP_TIME_MASK REG_GENMASK(24, 20)
46 #define EDP_PSR_TP2_TP3_TIME_MASK REG_GENMASK(9, 8)
51 #define EDP_PSR_TP4_TIME_MASK REG_GENMASK(7, 6)
53 #define EDP_PSR_TP1_TIME_MASK REG_GENMASK(5, 4)
58 #define EDP_PSR_IDLE_FRAMES_MASK REG_GENMASK(3, 0)
74 #define TGL_PSR_MASK REG_GENMASK(2, 0)
114 #define EDP_PSR_STATUS_LINK_MASK REG_GENMASK(27, 26)
125 #define EDP_PSR_STATUS_IDLE_MASK REG_GENMASK(3, 0)
131 #define EDP_PSR_PERF_CNT_MASK REG_GENMASK(23, 0)
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A Dintel_color_regs.h16 #define PALETTE_RED_MASK REG_GENMASK(23, 16)
17 #define PALETTE_GREEN_MASK REG_GENMASK(15, 8)
18 #define PALETTE_BLUE_MASK REG_GENMASK(7, 0)
20 #define PALETTE_10BIT_RED_LDW_MASK REG_GENMASK(23, 16)
21 #define PALETTE_10BIT_GREEN_LDW_MASK REG_GENMASK(15, 8)
22 #define PALETTE_10BIT_BLUE_LDW_MASK REG_GENMASK(7, 0)
24 #define PALETTE_10BIT_RED_EXP_MASK REG_GENMASK(23, 22)
26 #define PALETTE_10BIT_RED_UDW_MASK REG_GENMASK(17, 16)
30 #define PALETTE_10BIT_BLUE_EXP_MASK REG_GENMASK(7, 6)
32 #define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0)
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A Dintel_vdsc_regs.h39 #define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
95 #define DSC_PPS0_BPC_MASK REG_GENMASK(11, 8)
97 #define DSC_PPS0_VER_MINOR_MASK REG_GENMASK(7, 4)
99 #define DSC_PPS0_VER_MAJOR_MASK REG_GENMASK(3, 0)
103 #define DSC_PPS1_BPP_MASK REG_GENMASK(9, 0)
107 #define DSC_PPS2_PIC_WIDTH_MASK REG_GENMASK(31, 16)
108 #define DSC_PPS2_PIC_HEIGHT_MASK REG_GENMASK(15, 0)
113 #define DSC_PPS3_SLICE_WIDTH_MASK REG_GENMASK(31, 16)
114 #define DSC_PPS3_SLICE_HEIGHT_MASK REG_GENMASK(15, 0)
128 #define DSC_PPS5_SCALE_INC_INT_MASK REG_GENMASK(15, 0)
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A Dintel_sprite_regs.h16 #define DVS_FORMAT_MASK REG_GENMASK(26, 25)
25 #define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16)
46 #define DVS_POS_Y_MASK REG_GENMASK(31, 16)
48 #define DVS_POS_X_MASK REG_GENMASK(15, 0)
54 #define DVS_HEIGHT_MASK REG_GENMASK(31, 16)
56 #define DVS_WIDTH_MASK REG_GENMASK(15, 0)
70 #define DVS_ADDR_MASK REG_GENMASK(31, 12)
337 #define SP_SH_COS_MASK REG_GENMASK(9, 0)
359 #define SPCSC_IOFF_MASK REG_GENMASK(10, 0)
369 #define SPCSC_C0_MASK REG_GENMASK(14, 0)
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A Dintel_fbc_regs.h14 #define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16)
19 #define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5)
21 #define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
32 #define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2)
38 #define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0)
42 #define FBC_MOD_NUM_MASK REG_GENMASK(31, 1)
70 #define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6)
74 #define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
84 #define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0)
100 #define FBC_STRIDE_MASK REG_GENMASK(14, 0)
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A Dskl_watermark_regs.h20 #define MBUS_DBOX_BW_CREDIT_MASK REG_GENMASK(15, 14)
24 #define MBUS_DBOX_B_CREDIT_MASK REG_GENMASK(12, 8)
26 #define MBUS_DBOX_I_CREDIT_MASK REG_GENMASK(7, 5)
28 #define MBUS_DBOX_A_CREDIT_MASK REG_GENMASK(3, 0)
40 #define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26)
65 #define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19)
73 #define MTL_LATENCY_LEVEL_EVEN_MASK REG_GENMASK(12, 0)
74 #define MTL_LATENCY_LEVEL_ODD_MASK REG_GENMASK(28, 16)
77 #define MTL_LATENCY_QCLK_SAGV REG_GENMASK(12, 0)
80 #define LNL_ADDED_WAKE_TIME_MASK REG_GENMASK(28, 16)
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A Dintel_pfit_regs.h12 #define PFIT_PIPE_MASK REG_GENMASK(30, 29) /* 965+ */
14 #define PFIT_SCALING_MASK REG_GENMASK(28, 26) /* 965+ */
19 #define PFIT_FILTER_MASK REG_GENMASK(25, 24) /* 965+ */
23 #define PFIT_VERT_INTERP_MASK REG_GENMASK(11, 10) /* pre-965 */
26 #define PFIT_HORIZ_INTERP_MASK REG_GENMASK(7, 6) /* pre-965 */
32 #define PFIT_VERT_SCALE_MASK REG_GENMASK(31, 20) /* pre-965 */
49 #define PF_FILTER_MASK REG_GENMASK(24, 23)
58 #define PF_WIN_XSIZE_MASK REG_GENMASK(31, 16)
60 #define PF_WIN_YSIZE_MASK REG_GENMASK(15, 0)
66 #define PF_WIN_XPOS_MASK REG_GENMASK(31, 16)
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A Dbxt_dpio_phy_regs.h47 #define PORT_PLL_P1_MASK REG_GENMASK(15, 13)
49 #define PORT_PLL_P2_MASK REG_GENMASK(12, 8)
68 #define PORT_PLL_M2_INT_MASK REG_GENMASK(7, 0)
71 #define PORT_PLL_N_MASK REG_GENMASK(11, 8)
124 #define SUS_CLK_CONFIG REG_GENMASK(1, 0)
148 #define GRC_CODE_MASK REG_GENMASK(31, 24)
152 #define GRC_CODE_SLOW_MASK REG_GENMASK(15, 8)
154 #define GRC_CODE_NOM_MASK REG_GENMASK(7, 0)
191 #define LANE_STAGGER_MASK REG_GENMASK(4, 0)
215 #define MARGIN_000_MASK REG_GENMASK(23, 16)
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A Dintel_display_regs.h349 #define HTOTAL_MASK REG_GENMASK(31, 16)
351 #define HACTIVE_MASK REG_GENMASK(15, 0)
357 #define HBLANK_END_MASK REG_GENMASK(31, 16)
365 #define HSYNC_END_MASK REG_GENMASK(31, 16)
367 #define HSYNC_START_MASK REG_GENMASK(15, 0)
373 #define VTOTAL_MASK REG_GENMASK(31, 16)
375 #define VACTIVE_MASK REG_GENMASK(15, 0)
381 #define VBLANK_END_MASK REG_GENMASK(31, 16)
389 #define VSYNC_END_MASK REG_GENMASK(31, 16)
697 #define TU_SIZE_MASK REG_GENMASK(30, 25)
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A Dintel_dsb_regs.h27 #define DSB_MMIO_DEAD_CLOCKS_COUNT_MASK REG_GENMASK(15, 8)
29 #define DSB_MMIO_CYCLES_MASK REG_GENMASK(7, 0)
33 #define DSB_POLL_WAIT_MASK REG_GENMASK(30, 23)
35 #define DSB_POLL_COUNT_MASK REG_GENMASK(22, 15)
42 #define DSB_REQARB_SM_STATE_MASK REG_GENMASK(29, 27)
45 #define DSB_TLBTRANS_SM_STATE_MASK REG_GENMASK(21, 20)
47 #define DSB_POINTERS_SM_STATE_MASK REG_GENMASK(18, 17)
49 #define DSB_MMIO_ARB_SM_STATE_MASK REG_GENMASK(15, 13)
50 #define DSB_MMIO_INST_SM_STATE_MASK REG_GENMASK(11, 7)
51 #define DSB_RESET_SM_STATE_MASK REG_GENMASK(5, 4)
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A Dintel_combo_phy_regs.h29 #define SUS_CLOCK_CONFIG REG_GENMASK(1, 0)
34 #define PWR_DOWN_LN_MASK REG_GENMASK(7, 4)
60 #define PROCESS_INFO_MASK REG_GENMASK(28, 26)
64 #define VOLTAGE_INFO_MASK REG_GENMASK(25, 24)
92 #define LATENCY_OPTIM_MASK REG_GENMASK(3, 2)
116 #define RCOMP_SCALAR_MASK REG_GENMASK(7, 0)
125 #define POST_CURSOR_2_MASK REG_GENMASK(11, 6)
127 #define CURSOR_COEFF_MASK REG_GENMASK(5, 0)
140 #define RTERM_SELECT_MASK REG_GENMASK(5, 3)
147 #define O_LDO_REF_SEL_CRI REG_GENMASK(6, 1)
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A Dintel_pps_regs.h30 #define PP_SEQUENCE_MASK REG_GENMASK(29, 28)
35 #define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0)
48 #define PANEL_UNLOCK_MASK REG_GENMASK(31, 16)
50 #define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4)
58 #define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30)
64 #define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16)
65 #define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0)
69 #define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16)
70 #define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0)
74 #define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8)
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A Dintel_cursor_regs.h16 #define CURSOR_STRIDE_MASK REG_GENMASK(29, 28)
18 #define CURSOR_FORMAT_MASK REG_GENMASK(26, 24)
27 #define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28)
49 #define CURSOR_POS_Y_MASK REG_GENMASK(30, 16)
52 #define CURSOR_POS_X_MASK REG_GENMASK(14, 0)
60 #define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12)
62 #define CURSOR_WIDTH_MASK REG_GENMASK(9, 0)
68 #define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0)
83 #define CUR_WM_LINES_MASK REG_GENMASK(26, 14)
102 #define CUR_BUF_END_MASK REG_GENMASK(27, 16)
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A Di9xx_plane_regs.h18 #define DISP_FORMAT_MASK REG_GENMASK(29, 26)
34 #define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24)
59 #define DISP_POS_Y_MASK REG_GENMASK(31, 16)
61 #define DISP_POS_X_MASK REG_GENMASK(15, 0)
66 #define DISP_HEIGHT_MASK REG_GENMASK(31, 16)
68 #define DISP_WIDTH_MASK REG_GENMASK(15, 0)
73 #define DISP_ADDR_MASK REG_GENMASK(31, 12)
94 #define PRIM_POS_Y_MASK REG_GENMASK(31, 16)
96 #define PRIM_POS_X_MASK REG_GENMASK(15, 0)
101 #define PRIM_HEIGHT_MASK REG_GENMASK(31, 16)
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A Dintel_cx0_phy_regs.h53 #define XELPDP_PORT_M2P_DATA_MASK REG_GENMASK(23, 16)
56 #define XELPDP_PORT_M2P_ADDRESS_MASK REG_GENMASK(11, 0)
72 #define XELPDP_PORT_P2M_DATA_MASK REG_GENMASK(23, 16)
112 #define XELPDP_PORT_WIDTH_MASK REG_GENMASK(3, 1)
272 #define C10_VDR_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0)
306 #define PHY_C20_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0)
333 #define C20_PHY_TX_RATE REG_GENMASK(2, 0)
353 #define C20_MPLLA_TX_CLK_DIV_MASK REG_GENMASK(10, 8)
360 #define C20_MPLLB_TX_CLK_DIV_MASK REG_GENMASK(15, 13)
362 #define C20_REF_CLK_MPLLB_DIV_MASK REG_GENMASK(12, 10)
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A Dskl_universal_plane_regs.h83 #define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10)
96 #define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0)
109 #define PLANE_STRIDE__MASK REG_GENMASK(11, 0)
119 #define PLANE_POS_Y_MASK REG_GENMASK(31, 16)
121 #define PLANE_POS_X_MASK REG_GENMASK(15, 0)
131 #define PLANE_HEIGHT_MASK REG_GENMASK(31, 16)
133 #define PLANE_WIDTH_MASK REG_GENMASK(15, 0)
160 #define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12)
181 #define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16)
183 #define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0)
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A Dintel_vrr_regs.h20 #define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
31 #define VRR_VMAX_MASK REG_GENMASK(19, 0)
38 #define VRR_VMIN_MASK REG_GENMASK(15, 0)
45 #define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16)
47 #define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0)
60 #define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20)
77 #define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0)
84 #define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)
103 #define VRR_VSYNC_END_MASK REG_GENMASK(28, 16)
105 #define VRR_VSYNC_START_MASK REG_GENMASK(12, 0)
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/drivers/gpu/drm/xe/regs/
A Dxe_gt_regs.h21 #define MTL_CAGF_MASK REG_GENMASK(8, 0)
22 #define MTL_CC_MASK REG_GENMASK(12, 9)
40 #define GMD_ID_REVID REG_GENMASK(5, 0)
51 #define MCR_SLICE_MASK REG_GENMASK(30, 27)
62 #define LE_SSE_MASK REG_GENMASK(18, 17)
64 #define LE_COS_MASK REG_GENMASK(16, 15)
67 #define LE_PFM_MASK REG_GENMASK(13, 11)
69 #define LE_SCC_MASK REG_GENMASK(10, 8)
75 #define LE_LRUM_MASK REG_GENMASK(5, 4)
216 #define L3BANK_MASK REG_GENMASK(3, 0)
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A Dxe_mchbar_regs.h31 #define PKG_PWR_UNIT REG_GENMASK(3, 0)
32 #define PKG_ENERGY_UNIT REG_GENMASK(12, 8)
33 #define PKG_TIME_UNIT REG_GENMASK(19, 16)
38 #define TEMP_MASK REG_GENMASK(7, 0)
41 #define PWR_LIM_VAL REG_GENMASK(14, 0)
43 #define PWR_LIM REG_GENMASK(15, 0)
44 #define PWR_LIM_TIME REG_GENMASK(23, 17)
45 #define PWR_LIM_TIME_X REG_GENMASK(23, 22)
46 #define PWR_LIM_TIME_Y REG_GENMASK(21, 17)
A Dxe_oa_regs.h24 #define OAR_OACONTROL_COUNTER_SEL_MASK REG_GENMASK(3, 1)
33 #define OAG_OAGLBCTXCTRL_TIMER_PERIOD_MASK REG_GENMASK(7, 2)
38 #define OAG_OAHEADPTR_MASK REG_GENMASK(31, 6)
40 #define OAG_OATAILPTR_MASK REG_GENMASK(31, 6)
43 #define OABUFFER_SIZE_MASK REG_GENMASK(5, 3)
47 #define OAG_OACONTROL_OA_PES_DISAG_EN REG_GENMASK(27, 22)
48 #define OAG_OACONTROL_OA_CCS_SELECT_MASK REG_GENMASK(18, 16)
49 #define OAG_OACONTROL_OA_COUNTER_SEL_MASK REG_GENMASK(4, 2)
52 #define OA_OACONTROL_REPORT_BC_MASK REG_GENMASK(9, 9)
53 #define OA_OACONTROL_COUNTER_SIZE_MASK REG_GENMASK(8, 8)
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/drivers/gpu/drm/i915/
A Dintel_mchbar_regs.h82 #define MLTR_WM2_MASK REG_GENMASK(13, 8)
83 #define MLTR_WM1_MASK REG_GENMASK(5, 0)
204 #define PKG_PWR_UNIT REG_GENMASK(3, 0)
205 #define PKG_ENERGY_UNIT REG_GENMASK(12, 8)
206 #define PKG_TIME_UNIT REG_GENMASK(19, 16)
212 #define TEMP_MASK REG_GENMASK(7, 0)
216 #define RP0_CAP_MASK REG_GENMASK(7, 0)
217 #define RP1_CAP_MASK REG_GENMASK(15, 8)
218 #define RPN_CAP_MASK REG_GENMASK(23, 16)
221 #define RPE_MASK REG_GENMASK(15, 8)
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/drivers/gpu/drm/xe/
A Dxe_pcode_api.h12 #define PCODE_MB_PARAM2 REG_GENMASK(23, 16)
13 #define PCODE_MB_PARAM1 REG_GENMASK(15, 8)
14 #define PCODE_MB_COMMAND REG_GENMASK(7, 0)
61 #define MAJOR_VERSION_MASK REG_GENMASK(31, 16)
62 #define MINOR_VERSION_MASK REG_GENMASK(15, 0)
64 #define BUILD_VERSION_MASK REG_GENMASK(15, 0)
80 #define AUXINFO_REG_OFFSET REG_GENMASK(17, 15)
81 #define OVERFLOW_REG_OFFSET REG_GENMASK(14, 12)
85 #define BOOT_STATUS REG_GENMASK(3, 1)
90 #define AUXINFO_HISTORY_OFFSET REG_GENMASK(31, 29)
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/drivers/gpu/drm/i915/gt/
A Dintel_gt_regs.h26 #define MTL_CAGF_MASK REG_GENMASK(8, 0)
29 #define MTL_CC_MASK REG_GENMASK(10, 9)
80 #define MTL_MCR_GROUPID REG_GENMASK(11, 8)
81 #define MTL_MCR_INSTANCEID REG_GENMASK(3, 0)
293 #define VERT_WM_VAL REG_GENMASK(9, 0)
520 #define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? REG_GENMASK(6, 0) : REG_GENMASK(4, 0))
586 #define GT_L3_EXC_MASK REG_GENMASK(6, 4)
902 #define MSG_IDLE_FW_MASK REG_GENMASK(13, 9)
1150 #define THROTTLE_12_5 REG_GENMASK(4, 2)
1165 #define STACKID_CTRL REG_GENMASK(6, 5)
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