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Searched refs:REG_GENMASK8 (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/i915/display/
A Dintel_cx0_phy_regs.h237 #define C10_PLL2_MULTIPLIERL_MASK REG_GENMASK8(7, 0)
238 #define C10_PLL3_MULTIPLIERH_MASK REG_GENMASK8(3, 0)
240 #define C10_PLL9_FRACN_DENL_MASK REG_GENMASK8(7, 0)
241 #define C10_PLL10_FRACN_DENH_MASK REG_GENMASK8(7, 0)
246 #define C10_PLL15_TXCLKDIV_MASK REG_GENMASK8(2, 0)
247 #define C10_PLL15_HDMIDIV_MASK REG_GENMASK8(5, 3)
249 #define C10_PLL16_ANA_CPINT REG_GENMASK8(6, 0)
256 #define C10_PLL19_ANA_V2I_MASK REG_GENMASK8(5, 4)
261 #define C10_CMN3_TXVBOOST_MASK REG_GENMASK8(7, 5)
265 #define C10_TX1_TERMCTL_MASK REG_GENMASK8(7, 5)
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A Dintel_cx0_phy.c2960 disables = REG_GENMASK8(3, 0) >> lane_count; in intel_cx0_program_phy_lane()
2962 disables = REG_GENMASK8(3, 0) << lane_count; in intel_cx0_program_phy_lane()
2965 disables &= ~REG_GENMASK8(1, 0); in intel_cx0_program_phy_lane()
2966 disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1); in intel_cx0_program_phy_lane()
/drivers/gpu/drm/i915/
A Di915_reg_defs.h19 #define REG_GENMASK8(high, low) GENMASK_U8(high, low) macro

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