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Searched refs:REG_L1_PHYS (Results 1 – 3 of 3) sorted by relevance

/drivers/staging/media/ipu3/
A Dipu3-mmu.c44 #define REG_L1_PHYS (IMGU_REG_BASE + 0x304) /* 27-bit pfn */ macro
477 writel(pteval, mmu->base + REG_L1_PHYS); in imgu_mmu_init()
533 writel(pteval, mmu->base + REG_L1_PHYS); in imgu_mmu_resume()
/drivers/media/pci/intel/ipu6/
A Dipu6-mmu.c49 #define REG_L1_PHYS 0x0004 /* 27-bit pfn */ macro
75 readl(mmu->mmu_hw[i].base + REG_L1_PHYS); in tlb_invalidate()
489 mmu->mmu_hw[i].base + REG_L1_PHYS); in ipu6_mmu_hw_init()
/drivers/staging/media/ipu7/
A Dipu7-mmu.c49 #define REG_L1_PHYS 0x0004 /* 27-bit pfn */ macro

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