Searched refs:REG_MASK (Results 1 – 8 of 8) sorted by relevance
60 data = dither_depth_map[cfg->c0_bitdepth] & REG_MASK(2); in dpu_hw_pp_setup_dither()61 data |= (dither_depth_map[cfg->c1_bitdepth] & REG_MASK(2)) << 2; in dpu_hw_pp_setup_dither()62 data |= (dither_depth_map[cfg->c2_bitdepth] & REG_MASK(2)) << 4; in dpu_hw_pp_setup_dither()63 data |= (dither_depth_map[cfg->c3_bitdepth] & REG_MASK(2)) << 6; in dpu_hw_pp_setup_dither()69 data = (cfg->matrix[i] & REG_MASK(4)) | in dpu_hw_pp_setup_dither()70 ((cfg->matrix[i + 1] & REG_MASK(4)) << 4) | in dpu_hw_pp_setup_dither()71 ((cfg->matrix[i + 2] & REG_MASK(4)) << 8) | in dpu_hw_pp_setup_dither()72 ((cfg->matrix[i + 3] & REG_MASK(4)) << 12); in dpu_hw_pp_setup_dither()
15 #define REG_MASK(n) ((BIT(n)) - 1) macro
74 regmap_read(port->target, ocelot->map[target][reg & REG_MASK], &val); in ocelot_port_readl()86 regmap_write(port->target, ocelot->map[target][reg & REG_MASK], val); in ocelot_port_writel()131 regfield.reg = ocelot->map[target][reg & REG_MASK]; in ocelot_regfields_init()
929 WARN(ocelot->map[SYS][last & REG_MASK] >= ocelot->map[SYS][layout[i].reg & REG_MASK], in ocelot_prepare_stats_regions()931 last, ocelot->map[SYS][last & REG_MASK], in ocelot_prepare_stats_regions()932 layout[i].reg, ocelot->map[SYS][layout[i].reg & REG_MASK]); in ocelot_prepare_stats_regions()935 if (region && ocelot->map[SYS][layout[i].reg & REG_MASK] == in ocelot_prepare_stats_regions()936 ocelot->map[SYS][last & REG_MASK] + 4) { in ocelot_prepare_stats_regions()
83 *addr = ocelot->map[*target][reg & REG_MASK]; in ocelot_reg_to_target_addr()
11 #define REG_MASK(b) (BIT(b + 1) - 1) macro155 mask = REG_MASK(msb - lsb); in rtl2832_rd_demod_reg()185 mask = REG_MASK(msb - lsb); in rtl2832_wr_demod_reg()
22 #define REG_MASK 0xffffffff macro301 v = ~DMA_ENABLE & REG_MASK; in knav_dma_hw_destroy()
897 ocelot->map[GCB][GCB_MIIM_MII_STATUS & REG_MASK], in vsc9953_mdio_bus_alloc()
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