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Searched refs:REG_OFFSET (Results 1 – 9 of 9) sorted by relevance

/drivers/pinctrl/spear/
A Dpinctrl-plgpio.c28 #define REG_OFFSET(base, reg, pin) (base + reg + (pin / MAX_GPIO_PER_REG) \ macro
85 u32 reg_off = REG_OFFSET(0, reg, pin); in is_plgpio_set()
96 u32 reg_off = REG_OFFSET(0, reg, pin); in plgpio_reg_set()
106 u32 reg_off = REG_OFFSET(0, reg, pin); in plgpio_reg_reset()
350 reg_off = REG_OFFSET(0, plgpio->regs.eit, offset); in plgpio_irq_set_type()
/drivers/gpu/drm/amd/display/dmub/src/
A Ddmub_dcn301.c41 #define DMUB_SR(reg) REG_OFFSET(reg),
A Ddmub_dcn302.c41 #define DMUB_SR(reg) REG_OFFSET(reg),
A Ddmub_dcn303.c42 #define DMUB_SR(reg) REG_OFFSET(reg),
A Ddmub_dcn21.c41 #define DMUB_SR(reg) REG_OFFSET(reg),
A Ddmub_reg.h37 #define REG_OFFSET(reg_name) (BASE(mm##reg_name##_BASE_IDX) + mm##reg_name) macro
A Ddmub_dcn30.c42 #define DMUB_SR(reg) REG_OFFSET(reg),
A Ddmub_dcn20.c42 #define DMUB_SR(reg) REG_OFFSET(reg),
/drivers/pci/controller/
A Dpcie-brcmstb.c1270 const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8; in brcm_extend_rbus_timeout() local
1278 writel(216 * timeout_us, pcie->base + REG_OFFSET); in brcm_extend_rbus_timeout()

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