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Searched refs:REG_SET (Results 1 – 25 of 101) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/hubp/dcn30/
A Ddcn30_hubp.c57 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, in hubp3_set_vm_system_aperture_settings()
60 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, in hubp3_set_vm_system_aperture_settings()
125 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, in hubp3_program_surface_flip_and_addr()
129 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, in hubp3_program_surface_flip_and_addr()
166 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, in hubp3_program_surface_flip_and_addr()
174 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, in hubp3_program_surface_flip_and_addr()
243 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, in hubp3_program_surface_flip_and_addr()
251 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, in hubp3_program_surface_flip_and_addr()
259 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, in hubp3_program_surface_flip_and_addr()
297 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, in hubp3_program_surface_flip_and_addr()
[all …]
/drivers/gpu/drm/amd/display/dc/mpc/dcn10/
A Ddcn10_mpc.c68 REG_SET(MPCC_BG_R_CR[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
70 REG_SET(MPCC_BG_G_Y[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
72 REG_SET(MPCC_BG_B_CB[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
217 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); in mpc1_insert_plane()
304 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, in mpc1_remove_mpcc()
308 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, in mpc1_remove_mpcc()
318 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); in mpc1_remove_mpcc()
319 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); in mpc1_remove_mpcc()
384 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); in mpc1_mpc_init_single_inst()
385 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); in mpc1_mpc_init_single_inst()
[all …]
/drivers/gpu/drm/amd/display/dc/dpp/dcn35/
A Ddcn35_dpp.c77 REG_SET(FCNV_FP_BIAS_R, 0, FCNV_FP_BIAS_R, 0); in dpp35_program_bias_and_scale_fcnv()
78 REG_SET(FCNV_FP_BIAS_G, 0, FCNV_FP_BIAS_G, 0); in dpp35_program_bias_and_scale_fcnv()
79 REG_SET(FCNV_FP_BIAS_B, 0, FCNV_FP_BIAS_B, 0); in dpp35_program_bias_and_scale_fcnv()
81 REG_SET(FCNV_FP_SCALE_R, 0, FCNV_FP_SCALE_R, 0x1F000); in dpp35_program_bias_and_scale_fcnv()
82 REG_SET(FCNV_FP_SCALE_G, 0, FCNV_FP_SCALE_G, 0x1F000); in dpp35_program_bias_and_scale_fcnv()
83 REG_SET(FCNV_FP_SCALE_B, 0, FCNV_FP_SCALE_B, 0x1F000); in dpp35_program_bias_and_scale_fcnv()
85 REG_SET(FCNV_FP_BIAS_R, 0, FCNV_FP_BIAS_R, params->bias_red); in dpp35_program_bias_and_scale_fcnv()
86 REG_SET(FCNV_FP_BIAS_G, 0, FCNV_FP_BIAS_G, params->bias_green); in dpp35_program_bias_and_scale_fcnv()
87 REG_SET(FCNV_FP_BIAS_B, 0, FCNV_FP_BIAS_B, params->bias_blue); in dpp35_program_bias_and_scale_fcnv()
89 REG_SET(FCNV_FP_SCALE_R, 0, FCNV_FP_SCALE_R, params->scale_red); in dpp35_program_bias_and_scale_fcnv()
[all …]
/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
A Ddcn10_hubp.c618 REG_SET(BLANK_OFFSET_1, 0, in hubp1_program_deadline()
621 REG_SET(DST_DIMENSIONS, 0, in hubp1_program_deadline()
636 REG_SET(NOM_PARAMETERS_0, 0, in hubp1_program_deadline()
640 REG_SET(NOM_PARAMETERS_1, 0, in hubp1_program_deadline()
643 REG_SET(NOM_PARAMETERS_4, 0, in hubp1_program_deadline()
646 REG_SET(NOM_PARAMETERS_5, 0, in hubp1_program_deadline()
657 REG_SET(NOM_PARAMETERS_2, 0, in hubp1_program_deadline()
661 REG_SET(NOM_PARAMETERS_3, 0, in hubp1_program_deadline()
664 REG_SET(NOM_PARAMETERS_6, 0, in hubp1_program_deadline()
667 REG_SET(NOM_PARAMETERS_7, 0, in hubp1_program_deadline()
[all …]
/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
A Ddcn401_hubp.c226 REG_SET(BLANK_OFFSET_1, 0, in hubp401_program_deadline()
229 REG_SET(DST_DIMENSIONS, 0, in hubp401_program_deadline()
244 REG_SET(NOM_PARAMETERS_0, 0, in hubp401_program_deadline()
248 REG_SET(NOM_PARAMETERS_1, 0, in hubp401_program_deadline()
251 REG_SET(NOM_PARAMETERS_4, 0, in hubp401_program_deadline()
254 REG_SET(NOM_PARAMETERS_5, 0, in hubp401_program_deadline()
265 REG_SET(NOM_PARAMETERS_2, 0, in hubp401_program_deadline()
269 REG_SET(NOM_PARAMETERS_3, 0, in hubp401_program_deadline()
272 REG_SET(NOM_PARAMETERS_6, 0, in hubp401_program_deadline()
275 REG_SET(NOM_PARAMETERS_7, 0, in hubp401_program_deadline()
[all …]
/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
A Ddcn10_dpp_cm.c100 REG_SET(CM_GAMUT_REMAP_CONTROL, 0, in program_gamut_remap()
154 REG_SET( in program_gamut_remap()
269 REG_SET(CM_TEST_DEBUG_INDEX, 0, in dpp1_cm_program_color_matrix()
391 REG_SET(CM_MEM_PWR_CTRL, 0, in dpp1_cm_power_on_regamma_lut()
527 REG_SET(CM_TEST_DEBUG_INDEX, 0, in dpp1_program_input_csc()
560 REG_SET(CM_ICSC_CONTROL, 0, in dpp1_program_input_csc()
648 REG_SET(CM_MEM_PWR_CTRL, 0, in dpp1_power_on_degamma_lut()
744 REG_SET(CM_DGAM_LUT_DATA, 0, in dpp1_program_degamma_lut()
746 REG_SET(CM_DGAM_LUT_DATA, 0, in dpp1_program_degamma_lut()
748 REG_SET(CM_DGAM_LUT_DATA, 0, in dpp1_program_degamma_lut()
[all …]
/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/
A Ddcn31_hubbub.c203 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0, in hubbub31_program_urgent_watermarks()
213 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0, in hubbub31_program_urgent_watermarks()
257 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0, in hubbub31_program_urgent_watermarks()
301 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, 0, in hubbub31_program_urgent_watermarks()
345 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, 0, in hubbub31_program_urgent_watermarks()
912 REG_SET(DCN_VM_FB_LOCATION_BASE, 0, in hubbub31_init_dchub_sys_ctx()
914 REG_SET(DCN_VM_FB_LOCATION_TOP, 0, in hubbub31_init_dchub_sys_ctx()
916 REG_SET(DCN_VM_FB_OFFSET, 0, in hubbub31_init_dchub_sys_ctx()
918 REG_SET(DCN_VM_AGP_BOT, 0, in hubbub31_init_dchub_sys_ctx()
920 REG_SET(DCN_VM_AGP_TOP, 0, in hubbub31_init_dchub_sys_ctx()
[all …]
/drivers/gpu/drm/amd/display/dc/optc/dcn20/
A Ddcn20_optc.c142 REG_SET(OPTC_BYTES_PER_PIXEL, 0, in optc2_set_dsc_config()
176 REG_SET(OPTC_MEMORY_CONFIG, 0, in optc2_set_odm_bypass()
205 REG_SET(OPTC_MEMORY_CONFIG, 0, in optc2_set_odm_combine()
284 REG_SET(OTG_GLOBAL_CONTROL0, 0, in optc2_align_vblanks()
294 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc2_align_vblanks()
322 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc2_align_vblanks()
374 REG_SET(OTG_GLOBAL_CONTROL0, 0, in optc2_align_vblanks()
383 REG_SET(OTG_GLOBAL_CONTROL0, 0, in optc2_triplebuffer_lock()
386 REG_SET(OTG_VUPDATE_KEEPOUT, 0, in optc2_triplebuffer_lock()
404 REG_SET(OTG_VUPDATE_KEEPOUT, 0, in optc2_triplebuffer_unlock()
[all …]
/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/
A Ddcn32_hubbub.c184 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0, in hubbub32_program_urgent_watermarks()
198 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0, in hubbub32_program_urgent_watermarks()
208 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0, in hubbub32_program_urgent_watermarks()
228 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0, in hubbub32_program_urgent_watermarks()
242 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0, in hubbub32_program_urgent_watermarks()
252 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0, in hubbub32_program_urgent_watermarks()
272 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0, in hubbub32_program_urgent_watermarks()
286 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, 0, in hubbub32_program_urgent_watermarks()
296 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, 0, in hubbub32_program_urgent_watermarks()
330 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, 0, in hubbub32_program_urgent_watermarks()
[all …]
/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_vmid.c78 REG_SET(PAGE_TABLE_START_ADDR_HI32, 0, in dcn20_vmid_setup()
80 REG_SET(PAGE_TABLE_START_ADDR_LO32, 0, in dcn20_vmid_setup()
83 REG_SET(PAGE_TABLE_END_ADDR_HI32, 0, in dcn20_vmid_setup()
85 REG_SET(PAGE_TABLE_END_ADDR_LO32, 0, in dcn20_vmid_setup()
92 REG_SET(PAGE_TABLE_BASE_ADDR_HI32, 0, in dcn20_vmid_setup()
95 REG_SET(PAGE_TABLE_BASE_ADDR_LO32, 0, in dcn20_vmid_setup()
/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/
A Ddcn401_hubbub.c63 REG_SET(COMPBUF_RESERVED_SPACE, 0, in dcn401_init_crb()
80 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0, in hubbub401_program_urgent_watermarks()
92 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0, in hubbub401_program_urgent_watermarks()
101 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0, in hubbub401_program_urgent_watermarks()
110 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_MALL_A, 0, in hubbub401_program_urgent_watermarks()
124 REG_SET(DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A, 0, in hubbub401_program_urgent_watermarks()
133 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0, in hubbub401_program_urgent_watermarks()
145 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0, in hubbub401_program_urgent_watermarks()
154 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0, in hubbub401_program_urgent_watermarks()
163 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_MALL_B, 0, in hubbub401_program_urgent_watermarks()
[all …]
/drivers/gpu/drm/amd/display/dc/mpc/dcn20/
A Ddcn20_mpc.c142 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_output_csc()
182 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_output_csc()
198 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_ocsc_default()
241 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_ocsc_default()
278 REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0, in mpc20_power_on_ogam_lut()
392 REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, in mpc20_program_ogam_pwl()
394 REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, in mpc20_program_ogam_pwl()
396 REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, in mpc20_program_ogam_pwl()
413 REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0); in apply_DEDCN20_305_wa()
426 REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, in apply_DEDCN20_305_wa()
[all …]
/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
A Ddcn30_dpp_cm.c94 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].red_reg); in dpp3_program_gammcor_lut()
102 REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].red_reg); in dpp3_program_gammcor_lut()
106 REG_SET(CM_GAMCOR_LUT_INDEX, 0, CM_GAMCOR_LUT_INDEX, 0); in dpp3_program_gammcor_lut()
115 REG_SET(CM_GAMCOR_LUT_INDEX, 0, CM_GAMCOR_LUT_INDEX, 0); in dpp3_program_gammcor_lut()
141 REG_SET(CM_MEM_PWR_CTRL, 0, in dpp3_power_on_gamcor_lut()
162 REG_SET(CM_BIAS_CR_R, 0, CM_BIAS_CR_R, bias_params->cm_bias_cr_r); in dpp3_program_cm_bias()
211 REG_SET(CM_GAMCOR_LUT_INDEX, 0, CM_GAMCOR_LUT_INDEX, 0); in dpp3_configure_gamcor_lut()
226 REG_SET(CM_GAMCOR_CONTROL, 0, CM_GAMCOR_MODE, 0); in dpp3_program_gamcor_lut()
232 REG_SET(CM_GAMCOR_CONTROL, 0, CM_GAMCOR_MODE, 2); in dpp3_program_gamcor_lut()
323 REG_SET(CM_GAMUT_REMAP_CONTROL, 0, in program_gamut_remap()
[all …]
/drivers/gpu/drm/amd/display/dc/dwb/dcn30/
A Ddcn30_dwb_cm.c183 REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0); in dwb3_configure_ogam_lut()
198 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].red_reg); in dwb3_program_ogam_pwl()
208 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].red_reg); in dwb3_program_ogam_pwl()
212 REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0); in dwb3_program_ogam_pwl()
218 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].green_reg); in dwb3_program_ogam_pwl()
222 REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0); in dwb3_program_ogam_pwl()
228 REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].blue_reg); in dwb3_program_ogam_pwl()
242 REG_SET(DWB_OGAM_CONTROL, 0, DWB_OGAM_MODE, 0); in dwb3_program_ogam_lut()
249 REG_SET(DWB_OGAM_CONTROL, 0, DWB_OGAM_MODE, 2); in dwb3_program_ogam_lut()
311 REG_SET(DWB_GAMUT_REMAP_MODE, 0, in dwb3_program_gamut_remap()
[all …]
/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_transform.c499 REG_SET(DC_LB_MEMORY_SPLIT, 0, in dce60_transform_set_scaler()
502 REG_SET(DC_LB_MEM_SIZE, 0, in dce60_transform_set_scaler()
1276 REG_SET(OUTPUT_CSC_CONTROL, 0, in configure_graphics_mode()
1281 REG_SET(OUTPUT_CSC_CONTROL, 0, in configure_graphics_mode()
1288 REG_SET(OUTPUT_CSC_CONTROL, 0, in configure_graphics_mode()
1316 REG_SET(OUTPUT_CSC_CONTROL, 0, in configure_graphics_mode()
1321 REG_SET(OUTPUT_CSC_CONTROL, 0, in configure_graphics_mode()
1327 REG_SET(OUTPUT_CSC_CONTROL, 0, in configure_graphics_mode()
1333 REG_SET(OUTPUT_CSC_CONTROL, 0, in configure_graphics_mode()
1342 REG_SET(OUTPUT_CSC_CONTROL, 0, in configure_graphics_mode()
[all …]
A Ddce_ipp.c127 REG_SET(CUR_SURFACE_ADDRESS_HIGH, 0, in dce_ipp_cursor_set_attributes()
130 REG_SET(CUR_SURFACE_ADDRESS, 0, in dce_ipp_cursor_set_attributes()
178 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1); in dce_ipp_program_input_lut()
181 REG_SET(DC_LUT_WRITE_EN_MASK, 0, DC_LUT_WRITE_EN_MASK, 0x7); in dce_ipp_program_input_lut()
193 REG_SET(DC_LUT_RW_INDEX, 0, in dce_ipp_program_input_lut()
197 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
200 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
203 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
210 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0); in dce_ipp_program_input_lut()
A Ddce_mem_input.c506 REG_SET(GRPH_X_START, 0, in program_size_and_rotation()
509 REG_SET(GRPH_Y_START, 0, in program_size_and_rotation()
512 REG_SET(GRPH_X_END, 0, in program_size_and_rotation()
515 REG_SET(GRPH_Y_END, 0, in program_size_and_rotation()
518 REG_SET(GRPH_PITCH, 0, in program_size_and_rotation()
521 REG_SET(HW_ROTATION, 0, in program_size_and_rotation()
536 REG_SET(GRPH_X_START, 0, in dce60_program_size()
539 REG_SET(GRPH_Y_START, 0, in dce60_program_size()
542 REG_SET(GRPH_X_END, 0, in dce60_program_size()
545 REG_SET(GRPH_Y_END, 0, in dce60_program_size()
[all …]
/drivers/gpu/drm/amd/display/dc/hubp/dcn20/
A Ddcn20_hubp.c93 REG_SET(BLANK_OFFSET_1, 0, in hubp2_program_deadline()
96 REG_SET(DST_DIMENSIONS, 0, in hubp2_program_deadline()
111 REG_SET(NOM_PARAMETERS_0, 0, in hubp2_program_deadline()
115 REG_SET(NOM_PARAMETERS_1, 0, in hubp2_program_deadline()
118 REG_SET(NOM_PARAMETERS_4, 0, in hubp2_program_deadline()
121 REG_SET(NOM_PARAMETERS_5, 0, in hubp2_program_deadline()
132 REG_SET(NOM_PARAMETERS_2, 0, in hubp2_program_deadline()
136 REG_SET(NOM_PARAMETERS_3, 0, in hubp2_program_deadline()
139 REG_SET(NOM_PARAMETERS_6, 0, in hubp2_program_deadline()
142 REG_SET(NOM_PARAMETERS_7, 0, in hubp2_program_deadline()
[all …]
/drivers/gpu/drm/amd/display/dc/dpp/dcn20/
A Ddcn20_dpp_cm.c105 REG_SET(CM_DGAM_LUT_DATA, 0, in dpp2_program_degamma_lut()
107 REG_SET(CM_DGAM_LUT_DATA, 0, in dpp2_program_degamma_lut()
109 REG_SET(CM_DGAM_LUT_DATA, 0, in dpp2_program_degamma_lut()
170 REG_SET(CM_GAMUT_REMAP_CONTROL, 0, in program_gamut_remap()
207 REG_SET( in program_gamut_remap()
307 REG_SET(CM_ICSC_CONTROL, 0, CM_ICSC_MODE, 0); in dpp2_program_input_csc()
361 REG_SET(CM_ICSC_CONTROL, 0, in dpp2_program_input_csc()
371 REG_SET(CM_MEM_PWR_CTRL, 0, in dpp20_power_on_blnd_lut()
402 REG_SET(CM_BLNDGAM_LUT_DATA, 0, in dpp20_program_blnd_pwl()
404 REG_SET(CM_BLNDGAM_LUT_DATA, 0, in dpp20_program_blnd_pwl()
[all …]
/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/
A Ddcn21_hubbub.c113 REG_SET(DCN_VM_FB_LOCATION_BASE, 0, in hubbub21_init_dchub()
115 REG_SET(DCN_VM_FB_LOCATION_TOP, 0, in hubbub21_init_dchub()
117 REG_SET(DCN_VM_FB_OFFSET, 0, in hubbub21_init_dchub()
119 REG_SET(DCN_VM_AGP_BOT, 0, in hubbub21_init_dchub()
121 REG_SET(DCN_VM_AGP_TOP, 0, in hubbub21_init_dchub()
123 REG_SET(DCN_VM_AGP_BASE, 0, in hubbub21_init_dchub()
172 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0, in hubbub21_program_urgent_watermarks()
182 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0, in hubbub21_program_urgent_watermarks()
227 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0, in hubbub21_program_urgent_watermarks()
272 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, 0, in hubbub21_program_urgent_watermarks()
[all …]
/drivers/gpu/drm/amd/display/dc/mpc/dcn32/
A Ddcn32_mpc.c74 REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0, MPCC_MCM_1DLUT_MEM_PWR_DIS, power_on); in mpc32_power_on_blnd_lut()
87 REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0, in mpc32_power_on_blnd_lut()
136 REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0); in mpc32_configure_post1dlut()
241 REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0); in mpc32_program_post1dlut_pwl()
247 REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0); in mpc32_program_post1dlut_pwl()
253 REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0); in mpc32_program_post1dlut_pwl()
271 REG_SET(MPCC_MCM_1DLUT_CONTROL[mpcc_id], 0, MPCC_MCM_1DLUT_MODE, 0); in mpc32_program_post1dlut()
339 REG_SET(MPCC_MCM_SHAPER_LUT_INDEX[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_INDEX, 0); in mpc32_configure_shaper_lut()
692 REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0, in mpc32_power_on_shaper_3dlut()
723 REG_SET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_MODE, 0); in mpc32_program_shaper()
[all …]
/drivers/gpu/drm/amd/display/dc/optc/dcn10/
A Ddcn10_optc.c84 REG_SET(OTG_VSTARTUP_PARAM, 0, in optc1_program_global_sync()
91 REG_SET(OTG_VREADY_PARAM, 0, in optc1_program_global_sync()
99 REG_SET(OTG_STEREO_CONTROL, 0, in optc1_disable_stereo()
192 REG_SET(OTG_H_TOTAL, 0, in optc1_program_timing()
223 REG_SET(OTG_V_TOTAL, 0, in optc1_program_timing()
675 REG_SET(OTG_GLOBAL_CONTROL0, 0, in optc1_lock()
748 REG_SET(OTG_VERT_SYNC_CONTROL, 0, in optc1_disable_reset_trigger()
892 REG_SET(OTG_GLOBAL_CONTROL2, 0, in optc1_setup_manual_trigger()
935 REG_SET(OTG_V_TOTAL_MID, 0, in optc1_set_drr()
963 REG_SET(OTG_V_TOTAL_MAX, 0, in optc1_set_vtotal_min_max()
[all …]
/drivers/gpu/drm/amd/display/dc/hpo/dcn31/
A Ddcn31_hpo_dp_link_encoder.c213 REG_SET(DP_DPHY_SYM32_TP_CUSTOM0, 0, TP_CUSTOM, tp_custom); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
215 REG_SET(DP_DPHY_SYM32_TP_CUSTOM1, 0, TP_CUSTOM, tp_custom); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
217 REG_SET(DP_DPHY_SYM32_TP_CUSTOM2, 0, TP_CUSTOM, tp_custom); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
219 REG_SET(DP_DPHY_SYM32_TP_CUSTOM3, 0, TP_CUSTOM, tp_custom); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
221 REG_SET(DP_DPHY_SYM32_TP_CUSTOM4, 0, TP_CUSTOM, tp_custom); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
223 REG_SET(DP_DPHY_SYM32_TP_CUSTOM5, 0, TP_CUSTOM, tp_custom); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
225 REG_SET(DP_DPHY_SYM32_TP_CUSTOM6, 0, TP_CUSTOM, tp_custom); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
227 REG_SET(DP_DPHY_SYM32_TP_CUSTOM7, 0, TP_CUSTOM, tp_custom); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
229 REG_SET(DP_DPHY_SYM32_TP_CUSTOM8, 0, TP_CUSTOM, tp_custom); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
231 REG_SET(DP_DPHY_SYM32_TP_CUSTOM9, 0, TP_CUSTOM, tp_custom); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
[all …]
/drivers/gpu/drm/amd/display/dc/hubp/dcn21/
A Ddcn21_hubp.c95 REG_SET(VBLANK_PARAMETERS_5, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
103 REG_SET(VBLANK_PARAMETERS_6, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
111 REG_SET(FLIP_PARAMETERS_3, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
119 REG_SET(FLIP_PARAMETERS_4, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
122 REG_SET(FLIP_PARAMETERS_5, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
125 REG_SET(FLIP_PARAMETERS_6, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
242 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, in hubp21_set_vm_system_aperture_settings()
245 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, in hubp21_set_vm_system_aperture_settings()
647 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, in program_surface_flip_and_addr()
656 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, in program_surface_flip_and_addr()
[all …]
/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/
A Ddcn10_hubbub.c259 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0, in hubbub1_program_urgent_watermarks()
284 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0, in hubbub1_program_urgent_watermarks()
309 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0, in hubbub1_program_urgent_watermarks()
334 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0, in hubbub1_program_urgent_watermarks()
375 REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0, in hubbub1_program_stutter_watermarks()
391 REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0, in hubbub1_program_stutter_watermarks()
408 REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0, in hubbub1_program_stutter_watermarks()
424 REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0, in hubbub1_program_stutter_watermarks()
441 REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0, in hubbub1_program_stutter_watermarks()
457 REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0, in hubbub1_program_stutter_watermarks()
[all …]

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