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Searched refs:REG_SET_3 (Results 1 – 25 of 30) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
A Ddcn401_dpp_dscl.c253 REG_SET_3(SCL_COEF_RAM_TAP_SELECT, 0, in dpp401_dscl_set_scaler_filter()
674 REG_SET_3(DSCL_EASF_V_MODE, 0, in dpp401_dscl_program_easf_v()
717 REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG0, 0, in dpp401_dscl_program_easf_v()
789 REG_SET_3(DSCL_EASF_H_MODE, 0, in dpp401_dscl_program_easf_h()
990 REG_SET_3(ISHARP_NOISE_GAIN_PWL, 0, in dpp401_dscl_program_isharp()
996 REG_SET_3(ISHARP_LBA_PWL_SEG0, 0, in dpp401_dscl_program_isharp()
1000 REG_SET_3(ISHARP_LBA_PWL_SEG1, 0, in dpp401_dscl_program_isharp()
1004 REG_SET_3(ISHARP_LBA_PWL_SEG2, 0, in dpp401_dscl_program_isharp()
1008 REG_SET_3(ISHARP_LBA_PWL_SEG3, 0, in dpp401_dscl_program_isharp()
1012 REG_SET_3(ISHARP_LBA_PWL_SEG4, 0, in dpp401_dscl_program_isharp()
[all …]
/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_ipp.c102 REG_SET_3(CUR_COLOR1, 0, in dce_ipp_cursor_set_attributes()
107 REG_SET_3(CUR_COLOR2, 0, in dce_ipp_cursor_set_attributes()
187 REG_SET_3(DC_LUT_CONTROL, 0, in dce_ipp_program_input_lut()
226 REG_SET_3(DEGAMMA_CONTROL, 0, in dce_ipp_set_degamma()
A Ddce_abm.c148 REG_SET_3(DC_ABM1_HG_MISC_CTRL, 0, in dce_abm_init()
153 REG_SET_3(DC_ABM1_IPCSC_COEFF_SEL, 0, in dce_abm_init()
171 REG_SET_3(DC_ABM1_HGLS_REG_READ_PROGRESS, 0, in dce_abm_init()
A Ddmub_abm_lcd.c88 REG_SET_3(DC_ABM1_HG_MISC_CTRL, 0, in dmub_abm_init()
93 REG_SET_3(DC_ABM1_IPCSC_COEFF_SEL, 0, in dmub_abm_init()
111 REG_SET_3(DC_ABM1_HGLS_REG_READ_PROGRESS, 0, in dmub_abm_init()
/drivers/gpu/drm/amd/display/dc/optc/dcn30/
A Ddcn30_optc.c94 REG_SET_3(OTG_VUPDATE_KEEPOUT, 0, in optc3_lock_doublebuffer_enable()
147 REG_SET_3(OTG_BLANK_DATA_COLOR, 0, in optc3_program_blank_color()
152 REG_SET_3(OTG_BLANK_DATA_COLOR_EXT, 0, in optc3_program_blank_color()
254 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc3_set_odm_combine()
/drivers/gpu/drm/amd/display/dc/opp/dcn20/
A Ddcn20_opp.c224 REG_SET_3(DPG_RAMP_CONTROL, 0, in opp2_set_disp_pattern_generator()
235 REG_SET_3(DPG_RAMP_CONTROL, 0, in opp2_set_disp_pattern_generator()
246 REG_SET_3(DPG_RAMP_CONTROL, 0, in opp2_set_disp_pattern_generator()
/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
A Ddcn401_dsc.c221 REG_SET_3(DSCC_CONFIG0, 0, in dsc_write_to_registers()
245 REG_SET_3(DSCC_PPS_CONFIG0, 0, in dsc_write_to_registers()
279 REG_SET_3(DSCC_PPS_CONFIG6, 0, in dsc_write_to_registers()
296 REG_SET_3(DSCC_PPS_CONFIG10, 0, in dsc_write_to_registers()
/drivers/gpu/drm/amd/display/dc/optc/dcn20/
A Ddcn20_optc.c167 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc2_set_odm_bypass()
208 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc2_set_odm_combine()
430 REG_SET_3(OTG_VUPDATE_KEEPOUT, 0, in optc2_lock_doublebuffer_enable()
/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
A Ddcn20_dsc.c599 REG_SET_3(DSCC_CONFIG0, 0, in dsc_write_to_registers()
623 REG_SET_3(DSCC_PPS_CONFIG0, 0, in dsc_write_to_registers()
657 REG_SET_3(DSCC_PPS_CONFIG6, 0, in dsc_write_to_registers()
674 REG_SET_3(DSCC_PPS_CONFIG10, 0, in dsc_write_to_registers()
/drivers/gpu/drm/amd/display/dc/optc/dcn401/
A Ddcn401_optc.c117 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc401_set_odm_combine()
437 REG_SET_3(OTG_VUPDATE_KEEPOUT, 0, in optc401_set_vupdate_keepout()
/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
A Ddcn10_dpp.c307 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_cnv_setup()
313 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_cnv_setup()
A Ddcn10_dpp_dscl.c251 REG_SET_3(SCL_COEF_RAM_TAP_SELECT, 0, in dpp1_dscl_set_scaler_filter()
636 REG_SET_3(DSCL_AUTOCAL, 0, in dpp1_dscl_set_scaler_manual_scale()
/drivers/gpu/drm/amd/display/dmub/src/
A Ddmub_reg.h70 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ macro
/drivers/gpu/drm/amd/display/dc/optc/dcn314/
A Ddcn314_optc.c84 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc314_set_odm_combine()
/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/
A Ddcn32_mmhubbub.c89 REG_SET_3(MMHUBBUB_WARMUP_CONTROL_STATUS, 0, MMHUBBUB_WARMUP_EN, true, in mmhubbub32_warmup_mcif()
/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_mmhubbub.c89 REG_SET_3(MMHUBBUB_WARMUP_CONTROL_STATUS, 0, MMHUBBUB_WARMUP_EN, true, in mmhubbub3_warmup_mcif()
/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
A Ddcn401_hubp.c286 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, in hubp401_program_deadline()
291 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, in hubp401_program_deadline()
296 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, in hubp401_program_deadline()
/drivers/gpu/drm/amd/display/dc/optc/dcn10/
A Ddcn10_optc.c584 REG_SET_3(OTG_BLACK_COLOR, 0, in optc1_program_blank_color()
761 REG_SET_3(OTG_TRIGA_CNTL, 0, in optc1_enable_reset_trigger()
770 REG_SET_3(OTG_TRIGA_CNTL, 0, in optc1_enable_reset_trigger()
/drivers/gpu/drm/amd/display/dc/optc/dcn32/
A Ddcn32_optc.c79 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc32_set_odm_combine()
/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
A Ddcn10_hubp.c678 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, in hubp1_program_deadline()
683 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, in hubp1_program_deadline()
688 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, in hubp1_program_deadline()
/drivers/gpu/drm/amd/display/dc/optc/dcn31/
A Ddcn31_optc.c72 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc31_set_odm_combine()
/drivers/gpu/drm/amd/display/dc/hubp/dcn20/
A Ddcn20_hubp.c153 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, in hubp2_program_deadline()
158 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, in hubp2_program_deadline()
163 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, in hubp2_program_deadline()
698 REG_SET_3(DMDATA_QOS_CNTL, 0, in hubp2_dmdata_set_attributes()
/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_dwb_scl.c704 REG_SET_3(WBSCL_COEF_RAM_SELECT, 0, in wbscl_set_scaler_filter()
/drivers/gpu/drm/amd/display/dc/optc/dcn35/
A Ddcn35_optc.c92 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc35_set_odm_combine()
/drivers/gpu/drm/amd/display/dc/dio/dcn10/
A Ddcn10_link_encoder.c143 REG_SET_3(DP_DPHY_SYM0, 0, in program_pattern_symbols()
151 REG_SET_3(DP_DPHY_SYM1, 0, in program_pattern_symbols()

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