Home
last modified time | relevance | path

Searched refs:REG_SIZE (Results 1 – 25 of 37) sorted by relevance

12

/drivers/irqchip/
A Dqcom-irq-combiner.c24 #define REG_SIZE 32 macro
41 return reg * REG_SIZE + bit; in irq_nr()
82 struct combiner_reg *reg = combiner->regs + data->hwirq / REG_SIZE; in combiner_irq_chip_mask_irq()
84 clear_bit(data->hwirq % REG_SIZE, &reg->enabled); in combiner_irq_chip_mask_irq()
90 struct combiner_reg *reg = combiner->regs + data->hwirq / REG_SIZE; in combiner_irq_chip_unmask_irq()
92 set_bit(data->hwirq % REG_SIZE, &reg->enabled); in combiner_irq_chip_unmask_irq()
186 (reg->bit_width > REG_SIZE)) { in get_registers_cb()
192 vaddr = devm_ioremap(ctx->dev, reg->address, REG_SIZE); in get_registers_cb()
/drivers/hwmon/
A Dultra45_env.c38 #define REG_SIZE 0x42UL macro
265 p->regs = of_ioremap(&op->resource[0], 0, REG_SIZE, "pic16f747"); in env_probe()
289 of_iounmap(&op->resource[0], p->regs, REG_SIZE); in env_probe()
301 of_iounmap(&op->resource[0], p->regs, REG_SIZE); in env_remove()
/drivers/pinctrl/qcom/
A Dpinctrl-ipq5018.c12 #define REG_SIZE 0x1000 macro
31 .ctl_reg = REG_SIZE * id, \
32 .io_reg = 0x4 + REG_SIZE * id, \
33 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
34 .intr_status_reg = 0xc + REG_SIZE * id, \
35 .intr_target_reg = 0x8 + REG_SIZE * id, \
A Dpinctrl-ipq5332.c12 #define REG_SIZE 0x1000 macro
31 .ctl_reg = REG_SIZE * id, \
32 .io_reg = 0x4 + REG_SIZE * id, \
33 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
34 .intr_status_reg = 0xc + REG_SIZE * id, \
35 .intr_target_reg = 0x8 + REG_SIZE * id, \
A Dpinctrl-ipq5424.c13 #define REG_SIZE 0x1000 macro
32 .ctl_reg = REG_SIZE * id, \
33 .io_reg = 0x4 + REG_SIZE * id, \
34 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
35 .intr_status_reg = 0xc + REG_SIZE * id, \
36 .intr_target_reg = 0x8 + REG_SIZE * id, \
A Dpinctrl-ipq9574.c12 #define REG_SIZE 0x1000 macro
31 .ctl_reg = REG_SIZE * id, \
32 .io_reg = 0x4 + REG_SIZE * id, \
33 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
34 .intr_status_reg = 0xc + REG_SIZE * id, \
35 .intr_target_reg = 0x8 + REG_SIZE * id, \
A Dpinctrl-ipq8074.c12 #define REG_SIZE 0x1000 macro
31 .ctl_reg = REG_SIZE * id, \
32 .io_reg = 0x4 + REG_SIZE * id, \
33 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
34 .intr_status_reg = 0xc + REG_SIZE * id, \
35 .intr_target_reg = 0x8 + REG_SIZE * id, \
A Dpinctrl-ipq6018.c12 #define REG_SIZE 0x1000 macro
31 .ctl_reg = REG_SIZE * id, \
32 .io_reg = 0x4 + REG_SIZE * id, \
33 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
34 .intr_status_reg = 0xc + REG_SIZE * id, \
35 .intr_target_reg = 0x8 + REG_SIZE * id, \
A Dpinctrl-sdx55.c12 #define REG_SIZE 0x1000 macro
32 .ctl_reg = REG_SIZE * id, \
33 .io_reg = 0x4 + REG_SIZE * id, \
34 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
35 .intr_status_reg = 0xc + REG_SIZE * id, \
36 .intr_target_reg = 0x8 + REG_SIZE * id, \
A Dpinctrl-sdx65.c13 #define REG_SIZE 0x1000 macro
32 .ctl_reg = REG_BASE + REG_SIZE * id, \
33 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
34 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
35 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
36 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
A Dpinctrl-msm8909.c13 #define REG_SIZE 0x1000 macro
32 .ctl_reg = REG_SIZE * id, \
33 .io_reg = 0x4 + REG_SIZE * id, \
34 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
35 .intr_status_reg = 0xc + REG_SIZE * id, \
36 .intr_target_reg = 0x8 + REG_SIZE * id, \
A Dpinctrl-qcm2290.c12 #define REG_SIZE 0x1000 macro
32 .ctl_reg = REG_SIZE * id, \
33 .io_reg = 0x4 + REG_SIZE * id, \
34 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
35 .intr_status_reg = 0xc + REG_SIZE * id, \
36 .intr_target_reg = 0x8 + REG_SIZE * id, \
A Dpinctrl-sm4450.c12 #define REG_SIZE 0x1000 macro
32 .ctl_reg = REG_SIZE * id, \
33 .io_reg = 0x4 + REG_SIZE * id, \
34 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
35 .intr_status_reg = 0xc + REG_SIZE * id, \
36 .intr_target_reg = 0x8 + REG_SIZE * id, \
A Dpinctrl-sm7150.c26 #define REG_SIZE 0x1000 macro
46 .ctl_reg = REG_SIZE * id, \
47 .io_reg = 0x4 + REG_SIZE * id, \
48 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
49 .intr_status_reg = 0xc + REG_SIZE * id, \
50 .intr_target_reg = 0x8 + REG_SIZE * id, \
A Dpinctrl-msm8976.c15 #define REG_SIZE 0x1000 macro
34 .ctl_reg = REG_BASE + REG_SIZE * id, \
35 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
36 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
37 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
38 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
A Dpinctrl-qcs8300.c12 #define REG_SIZE 0x1000 macro
33 .ctl_reg = REG_SIZE * id, \
34 .io_reg = 0x4 + REG_SIZE * id, \
35 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
36 .intr_status_reg = 0xc + REG_SIZE * id, \
37 .intr_target_reg = 0x8 + REG_SIZE * id, \
A Dpinctrl-qdu1000.c14 #define REG_SIZE 0x1000 macro
34 .ctl_reg = REG_BASE + REG_SIZE * id, \
35 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
36 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
37 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
38 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
A Dpinctrl-sdm660.c25 #define REG_SIZE 0x1000 macro
45 .ctl_reg = REG_SIZE * id, \
46 .io_reg = 0x4 + REG_SIZE * id, \
47 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
48 .intr_status_reg = 0xc + REG_SIZE * id, \
49 .intr_target_reg = 0x8 + REG_SIZE * id, \
A Dpinctrl-sdx75.c12 #define REG_SIZE 0x1000 macro
18 .ctl_reg = REG_BASE + REG_SIZE * id, \
19 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
20 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
21 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
22 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
A Dpinctrl-sa8775p.c14 #define REG_SIZE 0x1000 macro
33 .ctl_reg = REG_BASE + REG_SIZE * id, \
34 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
35 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
36 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
37 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
A Dpinctrl-sar2130p.c13 #define REG_SIZE 0x1000 macro
33 .ctl_reg = REG_SIZE * id, \
34 .io_reg = 0x4 + REG_SIZE * id, \
35 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
36 .intr_status_reg = 0xc + REG_SIZE * id, \
37 .intr_target_reg = 0x8 + REG_SIZE * id, \
A Dpinctrl-sdm670.c17 #define REG_SIZE 0x1000 macro
36 .ctl_reg = base + REG_SIZE * id, \
37 .io_reg = base + 0x4 + REG_SIZE * id, \
38 .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \
39 .intr_status_reg = base + 0xc + REG_SIZE * id, \
40 .intr_target_reg = base + 0x8 + REG_SIZE * id, \
A Dpinctrl-sm6350.c13 #define REG_SIZE 0x1000 macro
32 .ctl_reg = REG_SIZE * id, \
33 .io_reg = 0x4 + REG_SIZE * id, \
34 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
35 .intr_status_reg = 0xc + REG_SIZE * id, \
36 .intr_target_reg = 0x8 + REG_SIZE * id, \
A Dpinctrl-sm6375.c14 #define REG_SIZE 0x1000 macro
33 .ctl_reg = REG_SIZE * id, \
34 .io_reg = REG_SIZE * id + 0x4, \
35 .intr_cfg_reg = REG_SIZE * id + 0x8, \
36 .intr_status_reg = REG_SIZE * id + 0xc, \
37 .intr_target_reg = REG_SIZE * id + 0x8, \
A Dpinctrl-milos.c13 #define REG_SIZE 0x1000 macro
35 .ctl_reg = REG_SIZE * id, \
36 .io_reg = 0x4 + REG_SIZE * id, \
37 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
38 .intr_status_reg = 0xc + REG_SIZE * id, \
39 .intr_target_reg = 0x8 + REG_SIZE * id, \

Completed in 60 milliseconds

12