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Searched refs:REG_STRUCT (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/amd/display/dc/irq/dcn351/
A Dirq_service_dcn351.c161 REG_STRUCT[base + reg_num].enable_mask = \
163 REG_STRUCT[base + reg_num].enable_value[0] = \
168 REG_STRUCT[base + reg_num].ack_mask = \
170 REG_STRUCT[base + reg_num].ack_value = \
175 REG_STRUCT[base].enable_mask = \
177 REG_STRUCT[base].enable_value[0] = \
179 REG_STRUCT[base].enable_value[1] = \
181 REG_STRUCT[base].ack_reg = SRI_DMUB(reg2),\
182 REG_STRUCT[base].ack_mask = \
184 REG_STRUCT[base].ack_value = \
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dcn35/
A Dirq_service_dcn35.c182 REG_STRUCT[base + reg_num].enable_mask = \
184 REG_STRUCT[base + reg_num].enable_value[0] = \
189 REG_STRUCT[base + reg_num].ack_mask = \
191 REG_STRUCT[base + reg_num].ack_value = \
196 REG_STRUCT[base].enable_mask = \
198 REG_STRUCT[base].enable_value[0] = \
200 REG_STRUCT[base].enable_value[1] = \
202 REG_STRUCT[base].ack_reg = SRI_DMUB(reg2),\
203 REG_STRUCT[base].ack_mask = \
205 REG_STRUCT[base].ack_value = \
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dcn36/
A Dirq_service_dcn36.c160 REG_STRUCT[base + reg_num].enable_mask = \
162 REG_STRUCT[base + reg_num].enable_value[0] = \
167 REG_STRUCT[base + reg_num].ack_mask = \
169 REG_STRUCT[base + reg_num].ack_value = \
174 REG_STRUCT[base].enable_mask = \
176 REG_STRUCT[base].enable_value[0] = \
178 REG_STRUCT[base].enable_value[1] = \
180 REG_STRUCT[base].ack_reg = SRI_DMUB(reg2),\
181 REG_STRUCT[base].ack_mask = \
183 REG_STRUCT[base].ack_value = \
[all …]
/drivers/gpu/drm/amd/display/dc/resource/dcn35/
A Ddcn35_resource.c816 #undef REG_STRUCT in dcn35_dpp_create()
848 #undef REG_STRUCT in dcn35_opp_create()
873 #undef REG_STRUCT in dcn31_aux_engine_create()
936 #undef REG_STRUCT in dcn31_i2c_hw_create()
959 #undef REG_STRUCT in dcn35_mpc_create()
983 #undef REG_STRUCT in dcn35_hubbub_create()
987 #undef REG_STRUCT in dcn35_hubbub_create()
1038 #undef REG_STRUCT in dcn35_timing_generator_create()
1079 #undef REG_STRUCT in dcn35_link_encoder_create()
1087 #undef REG_STRUCT in dcn35_link_encoder_create()
[all …]
/drivers/gpu/drm/amd/display/dc/resource/dcn351/
A Ddcn351_resource.c796 #undef REG_STRUCT in dcn35_dpp_create()
828 #undef REG_STRUCT in dcn35_opp_create()
853 #undef REG_STRUCT in dcn31_aux_engine_create()
916 #undef REG_STRUCT in dcn31_i2c_hw_create()
939 #undef REG_STRUCT in dcn35_mpc_create()
963 #undef REG_STRUCT in dcn35_hubbub_create()
967 #undef REG_STRUCT in dcn35_hubbub_create()
1018 #undef REG_STRUCT in dcn35_timing_generator_create()
1059 #undef REG_STRUCT in dcn35_link_encoder_create()
1067 #undef REG_STRUCT in dcn35_link_encoder_create()
[all …]
/drivers/gpu/drm/amd/display/dc/resource/dcn36/
A Ddcn36_resource.c797 #undef REG_STRUCT in dcn35_dpp_create()
829 #undef REG_STRUCT in dcn35_opp_create()
854 #undef REG_STRUCT in dcn31_aux_engine_create()
917 #undef REG_STRUCT in dcn31_i2c_hw_create()
940 #undef REG_STRUCT in dcn35_mpc_create()
964 #undef REG_STRUCT in dcn35_hubbub_create()
968 #undef REG_STRUCT in dcn35_hubbub_create()
1019 #undef REG_STRUCT in dcn35_timing_generator_create()
1060 #undef REG_STRUCT in dcn35_link_encoder_create()
1068 #undef REG_STRUCT in dcn35_link_encoder_create()
[all …]
/drivers/gpu/drm/amd/display/dc/resource/dcn321/
A Ddcn321_resource.c749 #undef REG_STRUCT in dcn321_aux_engine_create()
789 #undef REG_STRUCT in dcn321_i2c_hw_create()
837 #undef REG_STRUCT in dcn321_hubbub_create()
841 #undef REG_STRUCT in dcn321_hubbub_create()
892 #undef REG_STRUCT in dcn321_hubp_create()
924 #undef REG_STRUCT in dcn321_dpp_create()
951 #undef REG_STRUCT in dcn321_mpc_create()
976 #undef REG_STRUCT in dcn321_opp_create()
999 #undef REG_STRUCT in dcn321_timing_generator_create()
1040 #undef REG_STRUCT in dcn321_link_encoder_create()
[all …]
/drivers/gpu/drm/amd/display/dc/resource/dcn401/
A Ddcn401_resource.c749 #undef REG_STRUCT in dcn401_aux_engine_create()
788 #undef REG_STRUCT in dcn401_i2c_hw_create()
836 #undef REG_STRUCT in dcn401_hubbub_create()
840 #undef REG_STRUCT in dcn401_hubbub_create()
890 #undef REG_STRUCT in dcn401_hubp_create()
922 #undef REG_STRUCT in dcn401_dpp_create()
949 #undef REG_STRUCT in dcn401_mpc_create()
974 #undef REG_STRUCT in dcn401_opp_create()
996 #undef REG_STRUCT in dcn401_timing_generator_create()
1037 #undef REG_STRUCT in dcn401_link_encoder_create()
[all …]
/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource.c754 #undef REG_STRUCT in dcn32_aux_engine_create()
794 #undef REG_STRUCT in dcn32_i2c_hw_create()
842 #undef REG_STRUCT in dcn32_hubbub_create()
846 #undef REG_STRUCT in dcn32_hubbub_create()
897 #undef REG_STRUCT in dcn32_hubp_create()
929 #undef REG_STRUCT in dcn32_dpp_create()
956 #undef REG_STRUCT in dcn32_mpc_create()
981 #undef REG_STRUCT in dcn32_opp_create()
1004 #undef REG_STRUCT in dcn32_timing_generator_create()
1045 #undef REG_STRUCT in dcn32_link_encoder_create()
[all …]
/drivers/gpu/drm/amd/display/dmub/src/
A Ddmub_dcn351.c19 #define REG_STRUCT regs in dmub_srv_dcn351_regs_init() macro
21 #define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg); in dmub_srv_dcn351_regs_init()
26 #define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field); in dmub_srv_dcn351_regs_init()
30 #define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field); in dmub_srv_dcn351_regs_init()
33 #undef REG_STRUCT in dmub_srv_dcn351_regs_init()
A Ddmub_dcn36.c19 #define REG_STRUCT regs in dmub_srv_dcn36_regs_init() macro
21 #define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg); in dmub_srv_dcn36_regs_init()
26 #define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field); in dmub_srv_dcn36_regs_init()
30 #define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field); in dmub_srv_dcn36_regs_init()
33 #undef REG_STRUCT in dmub_srv_dcn36_regs_init()
A Ddmub_dcn35.c42 #define REG_STRUCT regs in dmub_srv_dcn35_regs_init() macro
44 #define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg); in dmub_srv_dcn35_regs_init()
49 #define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field); in dmub_srv_dcn35_regs_init()
53 #define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field); in dmub_srv_dcn35_regs_init()
56 #undef REG_STRUCT in dmub_srv_dcn35_regs_init()
A Ddmub_dcn32.c44 #define REG_STRUCT regs in dmub_srv_dcn32_regs_init() macro
46 #define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg); in dmub_srv_dcn32_regs_init()
51 #define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field); in dmub_srv_dcn32_regs_init()
55 #define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field); in dmub_srv_dcn32_regs_init()
59 #undef REG_STRUCT in dmub_srv_dcn32_regs_init()

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