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Searched refs:REG_UPDATE_2 (Results 1 – 25 of 85) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/dccg/dcn401/
A Ddcn401_dccg.c229 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg401_set_dtbclk_p_src()
238 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg401_set_dtbclk_p_src()
247 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg401_set_dtbclk_p_src()
256 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg401_set_dtbclk_p_src()
395 REG_UPDATE_2(SYMCLK32_LE_CNTL, in dccg401_enable_symclk32_le()
404 REG_UPDATE_2(SYMCLK32_LE_CNTL, in dccg401_enable_symclk32_le()
413 REG_UPDATE_2(SYMCLK32_LE_CNTL, in dccg401_enable_symclk32_le()
422 REG_UPDATE_2(SYMCLK32_LE_CNTL, in dccg401_enable_symclk32_le()
441 REG_UPDATE_2(SYMCLK32_LE_CNTL, in dccg401_disable_symclk32_le()
450 REG_UPDATE_2(SYMCLK32_LE_CNTL, in dccg401_disable_symclk32_le()
[all …]
/drivers/gpu/drm/amd/display/dc/dccg/dcn31/
A Ddcn31_dccg.c189 REG_UPDATE_2(SYMCLK32_SE_CNTL, in dccg31_enable_symclk32_se()
198 REG_UPDATE_2(SYMCLK32_SE_CNTL, in dccg31_enable_symclk32_se()
207 REG_UPDATE_2(SYMCLK32_SE_CNTL, in dccg31_enable_symclk32_se()
216 REG_UPDATE_2(SYMCLK32_SE_CNTL, in dccg31_enable_symclk32_se()
235 REG_UPDATE_2(SYMCLK32_SE_CNTL, in dccg31_disable_symclk32_se()
244 REG_UPDATE_2(SYMCLK32_SE_CNTL, in dccg31_disable_symclk32_se()
253 REG_UPDATE_2(SYMCLK32_SE_CNTL, in dccg31_disable_symclk32_se()
262 REG_UPDATE_2(SYMCLK32_SE_CNTL, in dccg31_disable_symclk32_se()
288 REG_UPDATE_2(SYMCLK32_LE_CNTL, in dccg31_enable_symclk32_le()
293 REG_UPDATE_2(SYMCLK32_LE_CNTL, in dccg31_enable_symclk32_le()
[all …]
/drivers/gpu/drm/amd/display/dc/dccg/dcn35/
A Ddcn35_dccg.c528 REG_UPDATE_2(SYMCLK32_SE_CNTL, in dccg35_set_symclk32_se_src_new()
533 REG_UPDATE_2(SYMCLK32_SE_CNTL, in dccg35_set_symclk32_se_src_new()
538 REG_UPDATE_2(SYMCLK32_SE_CNTL, in dccg35_set_symclk32_se_src_new()
631 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg35_set_dtbclk_p_src_new()
636 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg35_set_dtbclk_p_src_new()
641 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg35_set_dtbclk_p_src_new()
646 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg35_set_dtbclk_p_src_new()
1316 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg35_set_dtbclk_p_src()
1325 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg35_set_dtbclk_p_src()
1334 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg35_set_dtbclk_p_src()
[all …]
/drivers/gpu/drm/amd/display/dc/dio/dcn30/
A Ddcn30_dio_stream_encoder.c82 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, in enc3_update_hdmi_info_packet()
89 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, in enc3_update_hdmi_info_packet()
310 REG_UPDATE_2(DP_DSC_CNTL, in enc3_dp_set_dsc_config()
361 REG_UPDATE_2(DP_MSA_VBID_MISC, in enc3_dp_set_dsc_pps_info_packet()
633 REG_UPDATE_2(HDMI_CONTROL, in enc3_stream_encoder_hdmi_set_stream_attribute()
637 REG_UPDATE_2(HDMI_CONTROL, in enc3_stream_encoder_hdmi_set_stream_attribute()
644 REG_UPDATE_2(HDMI_CONTROL, in enc3_stream_encoder_hdmi_set_stream_attribute()
648 REG_UPDATE_2(HDMI_CONTROL, in enc3_stream_encoder_hdmi_set_stream_attribute()
654 REG_UPDATE_2(HDMI_CONTROL, in enc3_stream_encoder_hdmi_set_stream_attribute()
667 REG_UPDATE_2(HDMI_CONTROL, in enc3_stream_encoder_hdmi_set_stream_attribute()
[all …]
/drivers/gpu/drm/amd/display/dc/opp/dcn10/
A Ddcn10_opp.c78 REG_UPDATE_2(FMT_CONTROL, in opp1_set_spatial_dither()
82 REG_UPDATE_2(FMT_CONTROL, in opp1_set_spatial_dither()
89 REG_UPDATE_2(FMT_CONTROL, in opp1_set_spatial_dither()
213 REG_UPDATE_2(FMT_CLAMP_CNTL, in opp1_set_clamping()
219 REG_UPDATE_2(FMT_CLAMP_CNTL, in opp1_set_clamping()
224 REG_UPDATE_2(FMT_CLAMP_CNTL, in opp1_set_clamping()
229 REG_UPDATE_2(FMT_CLAMP_CNTL, in opp1_set_clamping()
235 REG_UPDATE_2(FMT_CLAMP_CNTL, in opp1_set_clamping()
255 REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL, in opp1_set_dyn_expansion()
270 REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL, in opp1_set_dyn_expansion()
[all …]
/drivers/gpu/drm/amd/display/dc/dccg/dcn32/
A Ddcn32_dccg.c123 REG_UPDATE_2(OTG_PIXEL_RATE_DIV, in dccg32_set_pixel_rate_div()
128 REG_UPDATE_2(OTG_PIXEL_RATE_DIV, in dccg32_set_pixel_rate_div()
133 REG_UPDATE_2(OTG_PIXEL_RATE_DIV, in dccg32_set_pixel_rate_div()
138 REG_UPDATE_2(OTG_PIXEL_RATE_DIV, in dccg32_set_pixel_rate_div()
165 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg32_set_dtbclk_p_src()
174 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg32_set_dtbclk_p_src()
183 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg32_set_dtbclk_p_src()
192 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg32_set_dtbclk_p_src()
290 REG_UPDATE_2(DPSTREAMCLK_CNTL, in dccg32_set_dpstreamclk()
295 REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN, in dccg32_set_dpstreamclk()
[all …]
/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_opp.c156 REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL, in dce60_set_truncation()
177 REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL, in dce60_set_truncation()
227 REG_UPDATE_2(FMT_CONTROL, in set_spatial_dither()
231 REG_UPDATE_2(FMT_CONTROL, in set_spatial_dither()
237 REG_UPDATE_2(FMT_CONTROL, in set_spatial_dither()
311 REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL, in set_temporal_dither()
481 REG_UPDATE_2(FMT_CONTROL, in set_pixel_encoding()
486 REG_UPDATE_2(FMT_CONTROL, in set_pixel_encoding()
512 REG_UPDATE_2(FMT_CONTROL, in dce60_set_pixel_encoding()
524 REG_UPDATE_2(FMT_CONTROL, in dce60_set_pixel_encoding()
[all …]
A Ddce_stream_encoder.c132 REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL, in dce110_update_generic_info_packet()
438 REG_UPDATE_2( in dce110_stream_encoder_dp_set_stream_attribute()
576 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
580 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
587 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
591 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
597 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
611 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
623 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
1323 REG_UPDATE_2(AFMT_60958_0, in dce110_se_setup_hdmi_audio()
[all …]
/drivers/gpu/drm/amd/display/dc/dccg/dcn314/
A Ddcn314_dccg.c123 REG_UPDATE_2(OTG_PIXEL_RATE_DIV, in dccg314_set_pixel_rate_div()
128 REG_UPDATE_2(OTG_PIXEL_RATE_DIV, in dccg314_set_pixel_rate_div()
133 REG_UPDATE_2(OTG_PIXEL_RATE_DIV, in dccg314_set_pixel_rate_div()
166 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg314_set_dtbclk_p_src()
175 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg314_set_dtbclk_p_src()
184 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg314_set_dtbclk_p_src()
193 REG_UPDATE_2(DTBCLK_P_CNTL, in dccg314_set_dtbclk_p_src()
263 REG_UPDATE_2(DPSTREAMCLK_CNTL, in dccg314_set_dpstreamclk()
268 REG_UPDATE_2(DPSTREAMCLK_CNTL, in dccg314_set_dpstreamclk()
273 REG_UPDATE_2(DPSTREAMCLK_CNTL, in dccg314_set_dpstreamclk()
[all …]
/drivers/gpu/drm/amd/display/dc/dio/dcn20/
A Ddcn20_stream_encoder.c81 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, in enc2_update_hdmi_info_packet()
88 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, in enc2_update_hdmi_info_packet()
95 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, in enc2_update_hdmi_info_packet()
102 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, in enc2_update_hdmi_info_packet()
109 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, in enc2_update_hdmi_info_packet()
270 REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL1, in enc2_update_gsp7_128_info_packet()
287 REG_UPDATE_2(DP_DSC_CNTL, in enc2_dp_set_dsc_config()
326 REG_UPDATE_2(DP_MSA_VBID_MISC, in enc2_dp_set_dsc_pps_info_packet()
337 REG_UPDATE_2(DP_SEC_CNTL, in enc2_dp_set_dsc_pps_info_packet()
385 REG_UPDATE_2(DME_CONTROL, in enc2_set_dynamic_metadata()
[all …]
/drivers/gpu/drm/amd/display/dc/optc/dcn10/
A Ddcn10_optc.c196 REG_UPDATE_2(OTG_H_SYNC_A, in optc1_program_timing()
210 REG_UPDATE_2(OTG_H_BLANK_START_END, in optc1_program_timing()
234 REG_UPDATE_2(OTG_V_SYNC_A, in optc1_program_timing()
282 REG_UPDATE_2(OTG_CONTROL, in optc1_program_timing()
383 REG_UPDATE_2(CONTROL, in optc1_set_vtg_params()
429 REG_UPDATE_2(OTG_BLANK_CONTROL, in optc1_unblank_crtc()
453 REG_UPDATE_2(OTG_BLANK_CONTROL, in optc1_blank_crtc()
496 REG_UPDATE_2(OTG_CLOCK_CONTROL, in optc1_enable_optc_clock()
508 REG_UPDATE_2(OTG_CLOCK_CONTROL, in optc1_enable_optc_clock()
544 REG_UPDATE_2(OTG_CONTROL, in optc1_enable_crtc()
[all …]
/drivers/gpu/drm/amd/display/dc/optc/dcn35/
A Ddcn35_optc.c127 REG_UPDATE_2(OTG_CONTROL, in optc35_enable_crtc()
175 REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0); in optc35_phantom_crtc_post_enable()
200 REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL, in optc35_configure_crc()
205 REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL, in optc35_configure_crc()
210 REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL, in optc35_configure_crc()
215 REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL, in optc35_configure_crc()
233 REG_UPDATE_2(OTG_CRC1_WINDOWA_X_CONTROL, in optc35_configure_crc()
238 REG_UPDATE_2(OTG_CRC1_WINDOWA_Y_CONTROL, in optc35_configure_crc()
243 REG_UPDATE_2(OTG_CRC1_WINDOWB_X_CONTROL, in optc35_configure_crc()
248 REG_UPDATE_2(OTG_CRC1_WINDOWB_Y_CONTROL, in optc35_configure_crc()
[all …]
/drivers/gpu/drm/amd/display/dc/dio/dcn314/
A Ddcn314_dio_stream_encoder.c198 REG_UPDATE_2(HDMI_CONTROL, in enc314_stream_encoder_hdmi_set_stream_attribute()
202 REG_UPDATE_2(HDMI_CONTROL, in enc314_stream_encoder_hdmi_set_stream_attribute()
209 REG_UPDATE_2(HDMI_CONTROL, in enc314_stream_encoder_hdmi_set_stream_attribute()
213 REG_UPDATE_2(HDMI_CONTROL, in enc314_stream_encoder_hdmi_set_stream_attribute()
219 REG_UPDATE_2(HDMI_CONTROL, in enc314_stream_encoder_hdmi_set_stream_attribute()
232 REG_UPDATE_2(HDMI_CONTROL, in enc314_stream_encoder_hdmi_set_stream_attribute()
244 REG_UPDATE_2(HDMI_CONTROL, in enc314_stream_encoder_hdmi_set_stream_attribute()
340 REG_UPDATE_2(DP_VID_TIMING, in enc314_stream_encoder_dp_unblank()
/drivers/gpu/drm/amd/display/dc/dio/dcn35/
A Ddcn35_dio_stream_encoder.c144 REG_UPDATE_2(HDMI_CONTROL, in enc35_stream_encoder_hdmi_set_stream_attribute()
148 REG_UPDATE_2(HDMI_CONTROL, in enc35_stream_encoder_hdmi_set_stream_attribute()
155 REG_UPDATE_2(HDMI_CONTROL, in enc35_stream_encoder_hdmi_set_stream_attribute()
159 REG_UPDATE_2(HDMI_CONTROL, in enc35_stream_encoder_hdmi_set_stream_attribute()
165 REG_UPDATE_2(HDMI_CONTROL, in enc35_stream_encoder_hdmi_set_stream_attribute()
178 REG_UPDATE_2(HDMI_CONTROL, in enc35_stream_encoder_hdmi_set_stream_attribute()
190 REG_UPDATE_2(HDMI_CONTROL, in enc35_stream_encoder_hdmi_set_stream_attribute()
320 REG_UPDATE_2(DP_VID_TIMING, in enc35_stream_encoder_dp_unblank()
/drivers/gpu/drm/amd/display/dc/dio/dcn32/
A Ddcn32_dio_stream_encoder.c156 REG_UPDATE_2(HDMI_CONTROL, in enc32_stream_encoder_hdmi_set_stream_attribute()
160 REG_UPDATE_2(HDMI_CONTROL, in enc32_stream_encoder_hdmi_set_stream_attribute()
167 REG_UPDATE_2(HDMI_CONTROL, in enc32_stream_encoder_hdmi_set_stream_attribute()
171 REG_UPDATE_2(HDMI_CONTROL, in enc32_stream_encoder_hdmi_set_stream_attribute()
177 REG_UPDATE_2(HDMI_CONTROL, in enc32_stream_encoder_hdmi_set_stream_attribute()
190 REG_UPDATE_2(HDMI_CONTROL, in enc32_stream_encoder_hdmi_set_stream_attribute()
202 REG_UPDATE_2(HDMI_CONTROL, in enc32_stream_encoder_hdmi_set_stream_attribute()
288 REG_UPDATE_2(DP_VID_TIMING, in enc32_stream_encoder_dp_unblank()
/drivers/gpu/drm/amd/display/dc/optc/dcn20/
A Ddcn20_optc.c69 REG_UPDATE_2(OTG_CONTROL, in optc2_enable_crtc()
315 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, in optc2_align_vblanks()
361 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, in optc2_align_vblanks()
417 REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1, in optc2_lock_doublebuffer_enable()
424 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, in optc2_lock_doublebuffer_enable()
440 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, in optc2_lock_doublebuffer_disable()
446 REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0, in optc2_lock_doublebuffer_disable()
/drivers/gpu/drm/amd/display/dc/dio/dcn401/
A Ddcn401_dio_stream_encoder.c156 REG_UPDATE_2(HDMI_CONTROL, in enc401_stream_encoder_hdmi_set_stream_attribute()
160 REG_UPDATE_2(HDMI_CONTROL, in enc401_stream_encoder_hdmi_set_stream_attribute()
167 REG_UPDATE_2(HDMI_CONTROL, in enc401_stream_encoder_hdmi_set_stream_attribute()
171 REG_UPDATE_2(HDMI_CONTROL, in enc401_stream_encoder_hdmi_set_stream_attribute()
177 REG_UPDATE_2(HDMI_CONTROL, in enc401_stream_encoder_hdmi_set_stream_attribute()
190 REG_UPDATE_2(HDMI_CONTROL, in enc401_stream_encoder_hdmi_set_stream_attribute()
202 REG_UPDATE_2(HDMI_CONTROL, in enc401_stream_encoder_hdmi_set_stream_attribute()
338 REG_UPDATE_2(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 1, DP_VID_STREAM_DIS_DEFER, 2); in enc401_stream_encoder_dp_unblank()
803 REG_UPDATE_2(DME_CONTROL, in enc401_set_dynamic_metadata()
/drivers/gpu/drm/amd/display/dc/dio/dcn10/
A Ddcn10_stream_encoder.c340 REG_UPDATE_2(DP_PIXEL_FORMAT, in enc1_stream_encoder_dp_set_stream_attribute()
519 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
525 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
534 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
540 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
548 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
563 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
575 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
999 REG_UPDATE_2(DP_VID_TIMING, in enc1_stream_encoder_dp_unblank()
1311 REG_UPDATE_2(AFMT_60958_0, in enc1_se_setup_hdmi_audio()
[all …]
/drivers/gpu/drm/amd/display/dc/hubp/dcn32/
A Ddcn32_hubp.c45 REG_UPDATE_2(UCLK_PSTATE_FORCE, in hubp32_update_force_pstate_disallow()
54 REG_UPDATE_2(UCLK_PSTATE_FORCE, in hubp32_update_force_cursor_pstate_disallow()
64 REG_UPDATE_2(DCHUBP_MALL_CONFIG, USE_MALL_SEL, mall_sel, in hubp32_update_mall_sel()
129 REG_UPDATE_2(CURSOR_SIZE, in hubp32_cursor_set_attributes()
/drivers/gpu/drm/amd/display/dc/dpp/dcn35/
A Ddcn35_dpp.c49 REG_UPDATE_2(DPP_CONTROL, in dpp35_dppclk_control()
54 REG_UPDATE_2(DPP_CONTROL, in dpp35_dppclk_control()
62 REG_UPDATE_2(DPP_CONTROL, in dpp35_dppclk_control()
/drivers/gpu/drm/amd/display/dc/opp/dcn20/
A Ddcn20_opp.c228 REG_UPDATE_2(DPG_CONTROL, in opp2_set_disp_pattern_generator()
239 REG_UPDATE_2(DPG_CONTROL, in opp2_set_disp_pattern_generator()
250 REG_UPDATE_2(DPG_CONTROL, in opp2_set_disp_pattern_generator()
279 REG_UPDATE_2(DPG_CONTROL, in opp2_set_disp_pattern_generator()
/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_afmt.c59 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, in afmt3_setup_hdmi_audio()
66 REG_UPDATE_2(AFMT_60958_0, in afmt3_setup_hdmi_audio()
181 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, in afmt3_setup_dp_audio()
/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
A Ddcn10_hubp.c46 REG_UPDATE_2(DCHUBP_CNTL, in hubp1_set_blank()
195 REG_UPDATE_2(DCSURF_SURFACE_PITCH, in hubp1_program_size()
199 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C, in hubp1_program_size()
219 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp1_program_rotation()
223 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp1_program_rotation()
227 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp1_program_rotation()
231 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp1_program_rotation()
254 REG_UPDATE_2(HUBPRET_CONTROL, in hubp1_program_pixel_format()
332 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp1_program_pixel_format()
337 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, in hubp1_program_pixel_format()
[all …]
/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_afmt.c64 REG_UPDATE_2(AFMT_MEM_PWR, AFMT_MEM_PWR_DIS, 0, AFMT_MEM_PWR_FORCE, 1); in afmt31_powerdown()
74 REG_UPDATE_2(AFMT_MEM_PWR, AFMT_MEM_PWR_DIS, 1, AFMT_MEM_PWR_FORCE, 0); in afmt31_poweron()
A Ddcn31_vpg.c59 REG_UPDATE_2(VPG_MEM_PWR, VPG_GSP_MEM_LIGHT_SLEEP_DIS, 0, VPG_GSP_LIGHT_SLEEP_FORCE, 1); in vpg31_powerdown()
74 REG_UPDATE_2(VPG_MEM_PWR, VPG_GSP_MEM_LIGHT_SLEEP_DIS, 1, VPG_GSP_LIGHT_SLEEP_FORCE, 0); in vpg31_poweron()

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