Home
last modified time | relevance | path

Searched refs:REG_UPDATE_4 (Results 1 – 25 of 25) sorted by relevance

/drivers/gpu/drm/amd/display/dc/hpo/dcn31/
A Ddcn31_hpo_dp_link_encoder.c110 REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG, in dcn31_hpo_dp_link_enc_set_link_test_pattern()
119 REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG, in dcn31_hpo_dp_link_enc_set_link_test_pattern()
128 REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG, in dcn31_hpo_dp_link_enc_set_link_test_pattern()
133 REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG, in dcn31_hpo_dp_link_enc_set_link_test_pattern()
142 REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG, in dcn31_hpo_dp_link_enc_set_link_test_pattern()
147 REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG, in dcn31_hpo_dp_link_enc_set_link_test_pattern()
156 REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG, in dcn31_hpo_dp_link_enc_set_link_test_pattern()
161 REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG, in dcn31_hpo_dp_link_enc_set_link_test_pattern()
170 REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG, in dcn31_hpo_dp_link_enc_set_link_test_pattern()
175 REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG, in dcn31_hpo_dp_link_enc_set_link_test_pattern()
[all …]
A Ddcn31_hpo_dp_stream_encoder.c674 REG_UPDATE_4(DP_SYM32_ENC_SDP_AUDIO_CONTROL0, in dcn31_hpo_dp_stream_enc_audio_disable()
/drivers/gpu/drm/amd/display/dc/optc/dcn35/
A Ddcn35_optc.c220 REG_UPDATE_4(OTG_CRC_CNTL, in optc35_configure_crc()
253 REG_UPDATE_4(OTG_CRC_CNTL, in optc35_configure_crc()
287 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, in optc35_setup_manual_trigger()
330 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, in optc35_set_drr()
359 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, in optc35_set_long_vtotal()
371 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, in optc35_set_long_vtotal()
391 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, in optc35_set_long_vtotal()
/drivers/gpu/drm/amd/display/dc/hubp/dcn30/
A Ddcn30_hubp.c138 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, in hubp3_program_surface_flip_and_addr()
268 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, in hubp3_program_surface_flip_and_addr()
324 REG_UPDATE_4(DCSURF_ADDR_CONFIG, in hubp3_program_tiling()
359 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, in hubp3_dcc_control()
/drivers/gpu/drm/amd/display/dc/dccg/dcn401/
A Ddcn401_dccg.c631 REG_UPDATE_4(DCCG_GATE_DISABLE_CNTL3, in dccg401_set_dp_dto()
639 REG_UPDATE_4(DCCG_GATE_DISABLE_CNTL3, in dccg401_set_dp_dto()
647 REG_UPDATE_4(DCCG_GATE_DISABLE_CNTL3, in dccg401_set_dp_dto()
655 REG_UPDATE_4(DCCG_GATE_DISABLE_CNTL3, in dccg401_set_dp_dto()
/drivers/gpu/drm/amd/display/dc/optc/dcn31/
A Ddcn31_optc.c209 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, in optc31_set_drr()
218 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, in optc31_set_drr()
/drivers/gpu/drm/amd/display/dc/optc/dcn401/
A Ddcn401_optc.c301 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, in optc401_setup_manual_trigger()
357 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, in optc401_set_drr()
/drivers/gpu/drm/amd/display/dc/optc/dcn301/
A Ddcn301_optc.c86 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, in optc301_set_drr()
/drivers/gpu/drm/amd/display/dmub/src/
A Ddmub_reg.h103 #define REG_UPDATE_4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \ macro
/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
A Ddcn10_hubp.c156 REG_UPDATE_4(DCSURF_TILING_CONFIG, in hubp1_program_tiling()
418 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, in hubp1_program_surface_flip_and_addr()
528 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, in hubp1_clear_tiling()
542 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, in hubp1_dcc_control()
/drivers/gpu/drm/amd/display/dc/hubp/dcn32/
A Ddcn32_hubp.c133 REG_UPDATE_4(CURSOR_CONTROL, in hubp32_cursor_set_attributes()
/drivers/gpu/drm/amd/display/dc/hubp/dcn20/
A Ddcn20_hubp.c321 REG_UPDATE_4(DCSURF_TILING_CONFIG, in hubp2_program_tiling()
416 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, in hubp2_clear_tiling()
430 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, in hubp2_dcc_control()
625 REG_UPDATE_4(CURSOR_CONTROL, in hubp2_cursor_set_attributes()
786 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, in hubp2_program_surface_flip_and_addr()
/drivers/gpu/drm/amd/display/dc/opp/dcn20/
A Ddcn20_opp.c260 REG_UPDATE_4(DPG_CONTROL, in opp2_set_disp_pattern_generator()
/drivers/gpu/drm/amd/display/dc/optc/dcn32/
A Ddcn32_optc.c264 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, in optc32_setup_manual_trigger()
/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_dmcu.c186 REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
621 REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK, in dcn10_dmcu_setup_psr()
A Ddce_aux.c242 value = REG_UPDATE_4(AUX_SW_DATA, in submit_channel_request()
A Ddce_mem_input.c622 REG_UPDATE_4(PRESCALE_GRPH_CONTROL, in program_grph_pixel_format()
A Ddce_link_encoder.c152 REG_UPDATE_4(DP_DPHY_CNTL, in disable_prbs_symbols()
/drivers/gpu/drm/amd/display/dc/optc/dcn20/
A Ddcn20_optc.c460 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, in optc2_setup_manual_trigger()
/drivers/gpu/drm/amd/display/dc/optc/dcn10/
A Ddcn10_optc.c1033 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, in optc1_set_test_pattern()
1133 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, in optc1_set_test_pattern()
/drivers/gpu/drm/amd/display/dc/dio/dcn401/
A Ddcn401_dio_stream_encoder.c579 REG_UPDATE_4(DP_PIXEL_FORMAT, in enc401_stream_encoder_dp_set_stream_attribute()
/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/
A Ddcn21_hubbub.c94 REG_UPDATE_4(DCHVM_CLK_CTRL, in dcn21_dchvm_init()
/drivers/gpu/drm/amd/display/dc/dio/dcn10/
A Ddcn10_link_encoder.c123 REG_UPDATE_4(DP_DPHY_CNTL, in disable_prbs_symbols()
/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
A Ddcn401_hubp.c450 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, in hubp401_program_surface_flip_and_addr()
/drivers/gpu/drm/amd/display/dc/inc/
A Dreg_helper.h245 #define REG_UPDATE_4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \ macro

Completed in 64 milliseconds