Searched refs:RING_CTL (Results 1 – 13 of 13) sorted by relevance
| /drivers/gpu/drm/i915/gt/ |
| A D | intel_ring_submission.c | 183 ENGINE_WRITE_FW(engine, RING_CTL, 0); in stop_ring()
184 ENGINE_POSTING_READ(engine, RING_CTL); in stop_ring()
262 ENGINE_WRITE_FW(engine, RING_CTL, in xcs_resume()
267 RING_CTL(engine->mmio_base), in xcs_resume()
294 ENGINE_READ(engine, RING_CTL), in xcs_resume()
295 ENGINE_READ(engine, RING_CTL) & RING_VALID, in xcs_resume()
364 ENGINE_READ_FW(engine, RING_CTL), in reset_prepare()
379 ENGINE_READ_FW(engine, RING_CTL), in reset_prepare()
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| A D | intel_engine_regs.h | 20 #define RING_CTL(base) _MMIO((base) + 0x3c) macro
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| A D | intel_gt.c | 146 intel_uncore_write(uncore, RING_CTL(base), 0); in init_unused_ring()
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| A D | intel_engine_cs.c | 2098 ENGINE_READ(engine, RING_CTL), in intel_engine_print_registers()
2099 ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : ""); in intel_engine_print_registers()
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| A D | selftest_lrc.c | 310 i915_mmio_reg_offset(RING_CTL(engine->mmio_base)), in live_lrc_fixed()
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| A D | intel_execlists_submission.c | 1970 ENGINE_READ(engine, RING_CTL), in process_csb()
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| /drivers/gpu/drm/xe/regs/ |
| A D | xe_engine_regs.h | 58 #define RING_CTL(base) XE_REG((base) + 0x3c) macro
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| /drivers/gpu/drm/i915/ |
| A D | i915_pmu.c | 362 val = ENGINE_READ_FW(engine, RING_CTL); in gen3_engine_sample()
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| A D | intel_gvt_mmio_table.c | 93 MMIO_RING_D(RING_CTL); in iterate_generic_mmio()
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| A D | i915_gpu_error.c | 1282 ee->ctl = ENGINE_READ(engine, RING_CTL); in engine_record_registers()
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| /drivers/gpu/drm/i915/gt/uc/ |
| A D | intel_guc_capture.c | 70 { RING_CTL(0), 0, 0, "CTL" }, \
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| /drivers/gpu/drm/xe/ |
| A D | xe_guc_capture.c | 115 { RING_CTL(0), REG_32BIT, 0, 0, 0, "RING_CTL"}, \
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| /drivers/gpu/drm/i915/gvt/ |
| A D | handlers.c | 2244 MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL); in init_generic_mmio_info()
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