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Searched refs:RING_CTX_TIMESTAMP (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/i915/gt/
A Dselftest_engine_pm.c97 cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4004); in __measure_timestamps()
103 cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4012); in __measure_timestamps()
A Dintel_engine_regs.h210 #define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */ macro
A Dintel_lrc.c1274 *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0)); in gen12_emit_timestamp_wa()
1280 *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0)); in gen12_emit_timestamp_wa()
A Dselftest_lrc.c350 i915_mmio_reg_offset(RING_CTX_TIMESTAMP(engine->mmio_base)), in live_lrc_fixed()
769 *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(rq->engine->mmio_base)); in create_timestamp()
A Dintel_workarounds.c1973 RING_CTX_TIMESTAMP(engine->mmio_base), in allow_read_ctx_timestamp()
/drivers/gpu/drm/xe/
A Dxe_reg_whitelist.c45 XE_RTP_ACTIONS(WHITELIST(RING_CTX_TIMESTAMP(0),
A Dxe_ring_ops.c239 dw[i++] = RING_CTX_TIMESTAMP(0).addr; in emit_copy_timestamp()
A Dxe_lrc.c2109 RING_CTX_TIMESTAMP(hwe->mmio_base)); in get_ctx_timestamp()
2112 RING_CTX_TIMESTAMP(hwe->mmio_base)); in get_ctx_timestamp()
/drivers/gpu/drm/xe/regs/
A Dxe_engine_regs.h160 #define RING_CTX_TIMESTAMP(base) XE_REG((base) + 0x3a8) macro
/drivers/gpu/drm/i915/
A Di915_cmd_parser.c688 REG32_IDX(RING_CTX_TIMESTAMP, BLT_RING_BASE),

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